DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hase et al (U.S. Pub #20050032347), in view of Fillion et al (U.S. Patent #5637922).
With respect to claim 1, Hase teaches a chip package structure, comprising:
a substrate (Fig. 2G, 10) having a first metal pad and a second metal pad (Fig. 2A, left and right portions of 11);
a first chip (Fig. 2G, 2 and Paragraph 58) disposed on the first metal pad;
an insulating layer (Fig. 2B, 3 and Paragraph 63) disposed on the substrate and partially covering the first metal pad, the second metal pad and the first chip; and
a plurality of routing layers (Fig. 2G, 6; Paragraph 75 and 78) disposed on the substrate and electrically connected to the second metal pad, and the first chip.
Hase does not teach that the routing layer is electrically connected to the first metal pad.
Fillion1997 teaches a routing layer that is electrically connected to a first metal pad.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulating layer and routing layer of Hase such that the routing layer is electrically connected to the first metal pad as taught by Fillion1997 in order to implement a half bridge device (Col 5 Ln 42-55).
With respect to claim 3, Hase teaches that a thickness of the insulating layer ranges from 0.5 um to 200 um (Paragraph 66).
With respect to claim 4, Hase teaches that the insulating layer is made of a photosensitive and thermosetting insulating material (Paragraph 65, e.g. epoxy).
With respect to claim 7, Hase does not teach a package at least partially covering the substrate, the first chip, the insulating layer, and the plurality of routing layers.
Fillion1997 teaches a package at least partially covering the substrate, the first chip, the insulating layer, and the plurality of routing layers (Col 4 Ln 28-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a package on the device of Hase as taught by Fillion1997 in order to achieve the predictable result of encapsulating the device and facilitating further processing steps (Col 4 Ln 28-29).
With respect to claim 8, Hase does not teach a second chip disposed on the second metal pad, wherein the plurality of routing layers are further electrically connected to the second chip.
Fillion1997 teaches a second chip (Fig. 10, 12b) disposed on the second metal pad (Fig. 10, 20b), wherein the plurality of routing layers (Fig. 10, 26) are electrically connected to the second chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second chip on the second pad Hase as taught by Fillion1997 in order to implement a half bridge device (Col 5 Ln 42-55).
With respect to claim 9, Hase does not teach a second chip disposed on the second metal pad, wherein the plurality of routing layers are electrically connected to the second chip.
Fillion1997 teaches a second chip (Fig. 10, 12b) disposed on the second metal pad (Fig. 10, 20b), wherein the plurality of routing layers (Fig. 10, 26) are electrically connected to the second chip.
It would have been obvious to one of ordinary skill in the before the effective filing date of the claimed invention to provide a second chip on the second pad Hase as taught by Fillion1997 in order to implement a half bridge device (Col 5 Ln 42-55).
With respect to claim 10, Fillion1997 teaches that the plurality of routing layers comprise a first conductive line, a second conductive line, a third conductive line, a fourth conductive line, and a fifth conductive line, and
the first conductive line (Fig. 9, 26e) is electrically connected to the first metal pad, the second conductive line (Fig. 9, 26a) is electrically connected to the first chip, the third conductive line (Fig. 9, 26d) is electrically connected to the first chip and the second metal pad, and the fourth conductive line and the fifth conductive line (Fig. 9, 26b and 26c) are electrically connected to the second chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second chip and routing lines as taught by Fillion1997 in order to implement a half bridge device (Col 5 Ln 42-55).
Claims 2, 3, 13-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hase et al (U.S. Pub #20050032347), in view of Fillion et al (U.S. Patent #6306680), in view of Fillion et al (U.S. Patent #5637922).
With respect to claim 13, Hase teaches a manufacturing method of a chip package structure, comprising:
providing a substrate (Fig. 2A, 10) having a first metal pad and a second metal pad (Fig. 2A, left and right portions of 11);
disposing a first chip (Fig. 2A, 2 and Paragraph 58) on the first metal pad;
forming an insulating layer (Fig. 2B, 3 and Paragraph 63) on the substrate, wherein the insulating layer covers the first metal pad, the second metal pad and the first chip;
forming a plurality of openings (Fig. 2C, 31 and Paragraph 69) on the insulating layer through an etching process to expose the second metal pad and the first chip;
forming a photoresist layer (Fig. 2E, 7 and Paragraph 74) to cover a portion of the insulating layer, the first metal pad, the second metal pad and the substrate through a photolithography process (Paragraph 27 and 74); and
forming a plurality of routing layers (Fig. 2G, 6; Paragraph 75 and 78) to cover a portion of the insulating layer that is not covered by the photoresist layer and filling the plurality of the openings.
Hase does not teach
forming a plurality of routing layers through an electroplating process.
Fillion2001 teaches
forming a plurality of routing layers through an electroplating process (Col 5 Ln 26-36). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the routing layer of Hase by electroplating as taught by Fillion2001 order to achieve the predictable result of provide copper material defined by the photoresist.
Hase does not teach that the openings on the insulating layer expose a portion of the first metal pad.
Fillion1997 teaches a routing layer that is electrically connected to a first metal pad.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulating layer of Hase to include openings to expose a portion of the first metal pad, such that the routing layer is electrically connected to the first metal pad as taught by Fillion1997 in order to implement a half bridge device (Col 5 Ln 42-55).
With respect to claims 2 and 14, Hase does not teach that the plurality of routing layers are made of copper.
Fillion2001 teaches that the plurality of routing layers are made of copper (Col 5 Ln 35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the routing layers of Hase to comprise copper as taught by Fillion2001 in order to achieve the predictable result of providing the routing layers by electroplating.
With respect to claims 3 and 15, Hase does not teach that a thickness of each of the plurality of routing layers ranges from 30 um to 300 um. Fillion teaches that a thickness of each of the plurality of routing layers ranges from 30 um to 300 um (Col 5 Ln 41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the routing layers of Hase to a thickness as taught by Fillion2001 in order to achieve the predictable result of providing the routing layers by electroplating.
With respect to claim 16, Hase teaches that the insulating layer is made of a photosensitive and thermosetting insulating material (Paragraph 65, e.g. epoxy).
With respect to claim 17, Hase teaches that a thickness of the insulating layer ranges from 0.5 um to 200 um (Paragraph 66).
With respect to claim 19, Hase does not teach forming a package at least partially covering the substrate, the first chip, the insulating layer and the plurality of routing layers.
Fillion1997 teaches a package at least partially covering the substrate, the first chip, the insulating layer, and the plurality of routing layers (Col 4 Ln 28-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a package on the device of Hase as taught by Fillion1997 in order to achieve the predictable result of encapsulating the device and facilitating further processing steps (Col 4 Ln 28-29).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over in Hase and Fillion1997, view of Hata et al (U.S. Pub #2005/0121777).
With respect to claim 6, Hase does not teach that a dielectric strength of the insulating layer is greater than 100 V/m.
Hata teaches a power device comprising a dielectric layer, wherein a dielectric strength of the insulating layer is greater than 100 V/m (Paragraph 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a dielectric layer having a dielectric strength of the insulating layer is greater than 100 V/m as taught by Hata in order to provide safety (Paragraph 100).
Claim 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over in Hase and Fillion1997, view of Hoegerl et al (U.S. Pub #2015/0155267)
With respect to claim 11, Hase and Fillion1997 do not teach a second chip, a third chip, and a fourth chip, wherein the substrate further has a third metal pad, a fourth metal pad, and a fifth metal pad; the second chip and the fourth chip are disposed on the second metal pad, the third chip is disposed on the first metal pad, the third metal pad, the fourth metal pad, and the fifth metal pad surround the first metal pad and the second metal pad, and the plurality of routing layers are further electrically connected to the second chip, the third chip, the fourth chip, the third metal pad, the fourth metal pad, and the fifth metal pad.
Hoegerl teaches
a second chip, a third chip, and a fourth chip (Fig. 6, chips 104), wherein the substrate further has a third metal pad, a fourth metal pad, and a fifth metal pad (Fig. 5, pads 114); the second chip and the fourth chip are disposed on the second metal pad, the third chip is disposed on the first metal pad, the third metal pad, the fourth metal pad, and the fifth metal pad surround the first metal pad and the second metal pad, and a plurality of routing layers (Fig. 5, 110, 120 etc.) are further electrically connected to the second chip, the third chip, the fourth chip, the third metal pad, the fourth metal pad, and the fifth metal pad.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide additional chip, pads and routing layer in the device of Hase and Fillion1997 as taught by Hoegerl in order to increase the power capacity of the device (Paragraph 45).
With respect to claim 12, Hoegerl (Figs. 5 and 6) teaches that the plurality of routing layers comprises a first conductive line, a second conductive line, a third conductive line, a fourth conductive line, a fifth conductive line, and a sixth conductive line; and wherein the first conductive line is electrically connected to the first metal pad, the second conductive line is electrically connected to the first chip and the fifth metal pad, the third conductive line is electrically connected to the first chip and the second metal pad, the fourth conductive line is electrically connected to the second chip, the fourth chip and the third metal pad, the fifth conductive line is electrically connected to the third chip and the second metal pad, and the sixth conductive line is electrically connected to the third chip, the fourth chip, and the fourth metal pad.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide additional chip, pads and routing layer in the device of Hase and Fillion1997 as taught by Hoegerl in order to increase the power capacity of the device (Paragraph 45).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over in Hase, Fillion2001, and Fillion1997, view of Hata et al (U.S. Pub #2005/0121777).
With respect to claim 18, Hase does not teach that a dielectric strength of the insulating layer is greater than 100 V/m.
Hata teaches a power device comprising a dielectric layer, wherein a dielectric strength of the insulating layer is greater than 100 V/m (Paragraph 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a dielectric layer having a dielectric strength of the insulating layer is greater than 100 V/m as taught by Hata in order to provide safety (Paragraph 100).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812
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