DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim(s) 6-7 and 11-18 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention II and species 2 of invention I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 15, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-5 and 8-10 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 1, as currently presented the claim requires “a first well region … having a first electrical property” and “a second well region … having the first electrical property”. The scope of the term “first electrical property” is unclear. Specifically, it is not clear which electrical property of the first region is being covered by the term, and as a result it is not clear which electrical property the second well region has that is the same as the first well region. Review of the specification suggest that the term electrical property is referring to conductivity type of the first well and the second well, such as, p-type or n-type. Accordingly, for purpose of compact prosecution, it will be assumed that the term “electrical property” is referring to conductivity type of the first well and the second well, where the two wells are the same conductivity type. Claims 2-5 and 8-10 which either directly or indirectly depend from claim 1 and which inherit issues of claim 1 are rejected for similar reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sonsky et al. (US 2018/0261767, hereinafter “Sonsky”) in view of Huang et al. (US 2008/0017948, hereinafter “Huang”).
Regarding claim 1, Sonsky teaches in Fig. 15 (shown below) and related text, a semiconductor device (100, Fig. 15 and ¶[0017]), comprising:
a substrate (12, Fig. 15 and ¶[0007]);
a first well region (18, Fig. 15 and ¶[0006]), disposed in the substrate and having a first electrical property;
a second well region (16, Fig. 15 and ¶[0006]), disposed in the substrate, separated from the first well region, and having an electrical property;
a first gate dielectric layer (108, Fig. 15 and ¶[0018]), disposed on the first well region and has a first thickness (Fig. 15 and ¶[0018]);
a second gate dielectric layer (106, Fig. 15 and ¶[0018]), disposed on the second well region, separated from the first gate dielectric layer, and having a second thickness less than the first thickness (Fig. 15 and ¶[0018]);
a first gate electrode (112, Fig. 15 and ¶[0018]), disposed on the first gate dielectric layer;
a second gate electrode (110, Fig. 15 and ¶[0018]), disposed on the second gate dielectric layer and separated from the first gate electrode;
a drain region (132, Fig. 15 and ¶[0020]), disposed in the first well region (18, Fig. 15); and
a source region (116, 130, Fig. 15 and ¶[0020]), disposed in the second well region (16, Fig. 15).
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Sonsky, however, does not explicitly teach that the electrical property of the second well is the first electrical property.
Huang, in a similar field of endeavor, teaches in Figs. 8A and 10 that a device with a symmetric structures, such as claimed, that includes well regions with the same electrical property (HVNW, Fig. 10 and ¶¶[0037]-[0039]) and a device with asymmetric structure that includes wells (26, 28, Fig. 8A and ¶[0038]) having two different electrical properties (¶¶[0024] and [0025]), similar to those disclosed by Sonsky, can be used in place of one another in order to meet specific design requirements (¶[0038]).
This since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second well region of Sonsky with the same electrical property as that of the first well region, as disclosed by Huang, in order to meet specific design requirements.
Regarding claim 3 (1), the combined teaching of Sonsky and Huang discloses wherein the first well region and the second well region are separated from each other by a native region of the substrate (Sonsky, 12, Fig. 15).
Regarding claim 8 (1), the combined teaching of Sonsky and Huang discloses wherein the first gate dielectric layer has a bottom surface substantially flush with a bottom surface of the second gate dielectric layer (Sonsky, Fig. 15), and the first gate electrode and the second gate electrode include polysilicon (Huang, ¶[0032]).
Regarding claim 9 (1), the combined teaching of Sonsky and Huang discloses wherein a contact terminal (Sonsky, 136, Fig. 15 and ¶[0021]) of the source region (116, 130, Fig. 15 and ¶[0020]) is adjacent to the second gate dielectric layer (106, Fig. 15 and ¶[0018]), and there is a distance between a contact terminal (136, Fig. 15 and ¶[0021]) of the drain region (132, Fig. 15) and the first gate dielectric layer (108, Fig. 15 and ¶[0018]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sonsky and Huang as applied to claim 1 above, and further in view of Terada et al. (US 2008/0303968, hereinafter “Terada”).
Regarding claim 10 (1), the combined teaching of Sonsky and Huang was discussed above in the rejection of claim 1, and further comprises a teaching of the first gate electrode and the second gate electrode being electrically connected to one another (Sonsky, ¶[0023]). While Sonsky and Huang do not explicitly teach that
the first gate electrode and the second gate electrode are electrically connected by a metal wiring disposed on them, disposing a metal wiring on the elements of a transistor, such as source, drain and gate, so as to connect them to other elements is well-known in the art as evidenced by Terada (Fig. 2). Namely, Terada teaches that in order to connect a transistor to other elements of a semiconductor device (including other transistors), wirings, such as LL1 or HL1 can be formed on the transistor. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the two gates disclosed by Sonsky and Huang, using wring disclosed by Terada, as doing so would amount to nothing more than using known wiring structures to connect a transistor to other elements of semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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