DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on July 30, 2026, has been entered. No claim(s) has/have been canceled and claim(s) 19-23 has/have been added. Therefore, claim(s) 1-23 are pending in the application with claims 6-7 and 11-18 withdrawn from consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 19 and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Terada et al. (US 2008/0303968, hereinafter “Terada”, previously cited).
Regarding 1, Terada teaches in Fig. 2 (shown below) and related text a semiconductor device (Fig. 2 and ¶[0021]), comprising:
a substrate (1S, Fig. 2 and ¶[0069]);
a first well region (e.g. well 4 on the right of Fig. 2, Fig. 2 and ¶[0075]), disposed in the substrate (1S, Fig. 2) and having a first conductivity type (e.g. p-type, ¶[0075]);
a second well region (e.g. well 4 on the left of Fig. 2 or well 5 and ¶[0075]), disposed in the substrate (1S, Fig. 2), separated from the first well region (e.g. well 4 on the right, Fig. 2), and having the first conductivity type (¶[0075]);
a first gate dielectric layer (8, Fig. 15 and ¶[0082]), disposed on the first well region (e.g. well 4 on the right of Fig. 2) and has a first thickness (Fig. 2 and ¶[0082]);
a second gate dielectric layer (7, Fig. 2 and ¶[0082]), disposed on the second well region (e.g. well 4 on the left of Fig. 2), separated from the first gate dielectric layer (8, Fig. 2), and having a second thickness less than the first thickness (Fig. 2 and ¶[0082]);
a first gate electrode (10b, Fig. 2 and ¶[0077]), disposed on the first gate dielectric layer (8, Fig. 2);
a second gate electrode (10a, Fig. 2 and ¶[0082]), disposed on the second gate dielectric layer (7, Fig. 2) and separated from the first gate electrode (10b, Fig. 2);
a drain region (14, Fig. 2 and ¶[0096]), disposed in the first well region (e.g. well 4 on the right of Fig. 2); and
a source region (11, 13, Fig. 2 and ¶[0083]), disposed in the second well region (e.g. well 4 on the left of Fig. 2).
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Regarding claim 2 (1), Terada teaches wherein the first well region (e.g. well 4 on the right of Fig. 2) has a doping concentration smaller than that of the second well region (e.g. well 5, Fig. 2 and ¶¶[00081]-[0082], where it is noted that well 5 includes additional p-type dopant to that already introduced into well 4 so it would have higher concentration of dopant than well 4).
Regarding claim 3 (1), Terada teaches wherein the first well region (e.g. well 4 on the right of Fig. 2 and ¶[0075]) and the second well region (e.g. well 4 on the left of Fig. 2 or well 5, Fig. 2 and ¶[0075]) are separated from each other by a native region of the substrate (i.e. portion of 1S, Fig. 2).
Regarding claim 19 (1), Terada teaches wherein the drain region (13, Fig. 2) is disposed in the first well region (e.g. well 4 on the left of Fig. 2) and space apart from the first gate dielectric layer (7, Fig. 2), and the source region (6, Fig. 2) is disposed in the second well region (e.g. well 4 on the right of Fig. 2) and adjacent to the second gate dielectric layer (8, Fig. 2).
Regarding claim 23 (1), Terada teaches the first gate electrode (10a, Fig. 2 and ¶[0082]) and the second gate electrode (10b, Fig. 2 and ¶[0076]) include polysilicon (¶¶[0076] and [0082]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sonsky et al. (US 2018/0261676, hereinafter “Sonsky”, previously cited) in view of Huang et al. (US 2008/0017948, hereinafter “Huang”, previously cited).
Regarding claim 1, Sonsky teaches in Fig. 15 (shown below) and related text, a semiconductor device (100, Fig. 15 and ¶[0017]), comprising:
a substrate (12, Fig. 15 and ¶[0007]);
a first well region (18, Fig. 15 and ¶[0006]), disposed in the substrate and having a first electrical property;
a second well region (16, Fig. 15 and ¶[0006]), disposed in the substrate, separated from the first well region, and having an electrical property;
a first gate dielectric layer (108, Fig. 15 and ¶[0018]), disposed on the first well region and has a first thickness (Fig. 15 and ¶[0018]);
a second gate dielectric layer (106, Fig. 15 and ¶[0018]), disposed on the second well region, separated from the first gate dielectric layer, and having a second thickness less than the first thickness (Fig. 15 and ¶[0018]);
a first gate electrode (112, Fig. 15 and ¶[0018]), disposed on the first gate dielectric layer;
a second gate electrode (110, Fig. 15 and ¶[0018]), disposed on the second gate dielectric layer and separated from the first gate electrode;
a drain region (132, Fig. 15 and ¶[0020]), disposed in the first well region (18, Fig. 15); and
a source region (116, 130, Fig. 15 and ¶[0020]), disposed in the second well region (16, Fig. 15).
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Sonsky, however, does not explicitly teach that the conductivity type of the second well region is the same as the conductivity type of the first well region.
Huang, in a similar field of endeavor, teaches in Figs. 8A and 10 that a device with a symmetric structures (Fig. 10) that includes well regions with the same conductivity type (HVNW, Fig. 10 and ¶¶[0037]-[0039]) with a region of an opposite conductivity type (HVPW, Fig. 10 and ¶[0038]) therebetween, and a device with asymmetric structure that includes wells (26, 28, Fig. 8A and ¶[0038]) having two different conductivity types (¶¶[0024] and [0025]), similar to that disclosed by Sonsky, are well-known alternatives that can be used depending on specific design requirements (¶[0038]).
This since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the symmetric device that includes first and second well regions of the same first conductivity type, with the region of second conductivity type, therebetween, as disclosed by Huang, in place of the asymmetric device disclosed by Sonsky, in order to meet specific design requirements for the device.
Regarding claim 3 (1), the combined teaching of Sonsky and Huang discloses wherein the first well region, and the second well region are separated from each other by a native region of the substrate (Sonsky, part of substrate 12, Fig. 15).
Regarding claim 8 (1), the combined teaching of Sonsky and Huang discloses wherein the first gate dielectric layer has a bottom surface substantially flush with a bottom surface of the second gate dielectric layer (Sonsky, Fig. 15).
Regarding claim 9 (1), the combined teaching of Sonsky and Huang discloses wherein a contact terminal (Sonsky, 136, Fig. 15 and ¶[0021]) of the source region (116, 130, Fig. 15 and ¶[0020]) is adjacent to the second gate dielectric layer (106, Fig. 15 and ¶[0018]), and there is a distance between a contact terminal (136, Fig. 15 and ¶[0021]) of the drain region (132, Fig. 15) and the first gate dielectric layer (108, Fig. 15 and ¶[0018]).
Claim(s) 10 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sonsky and Huang as applied to claim 1 above, and further in view of Chu et al. (US 2021/0098342, hereinafter “Chu”).
Regarding claim 10 (1), the combined teaching of Sonsky and Huang was discussed above in the rejection of claim 1 and further comprises a teaching of the first gate electrode and the second gate electrode being electrically connected to one another (Sonsky, ¶[0023]). While Sonsky and Huang do not explicitly teach that
the first gate electrode and the second gate electrode are electrically connected by a metal wiring disposed on them, disposing a metal wiring on the elements of a transistor, such as source, drain and gate, so as to connect them to other elements is well-known in the art as evidenced by Chu (Fig. 6). Namely, Chu teaches that two different gate structures (GS1, GS2, Fig. 6 and ¶[0027]) can be connected to one another by a metal wiring (L1(M1), Fig. 6 and ¶[0031]) disposed on a first gate electrode (GS1, Fig. 6) and a second gate electrode (GS2, Fig. 6) to electrically connect the two. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the two gates disclosed by Sonsky and Huang, using wring disclosed by Chu, as doing so would amount to nothing more than using known wiring structures to connect two gate electrodes.
Regarding claim 22 (10), the combined teaching of Sonsky, Huang and Chu discloses wherein the metal wiring (Chu, L1(M1), Fig. 6) directly connects a top surface of the first gate electrode (GS1/GC1, Fig. 6) to a top surface of the second gate electrode (GS2/GC2, Fig. 6).
Allowable Subject Matter
Claim(s) 4-5 and 20-21 is/are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 4, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor device particularly characterized by a third well region in which first well and second well regions, as well as the native region, are disposed, in combination with all other elements of the semiconductor device recited in the claim(s). Claim(s) 5 and 20-21, which either directly or indirectly depend from claim(s) 4, and which include all of the limitations recited in claim(s) 4, is/are allowed for similar reasons.
Response to Arguments
Applicant's arguments filed on July 30, 2026, have been fully considered but they are not persuasive.
The applicant argues on pages 8-12 of the filed response that “[t]here would be no motivation for persons with ordinary skill in the art to combine the cited references "Sonsky" and "Huang" in a manner required meeting the claimed limitations of the amended independent claim 1 of the present application”. Specifically, the applicant argues that “[i]t would not be reasonable, possible and logical "... to form the second well region of Sonsky with the same electrical property as that of the first well region, as disclosed by Huang...", as alleged by the Office Action in page 5. As explicitly suggested by "Sonsky" a semiconductor device 100 in which "...well 16 is a P-type well and well 18 is an N-type well..." (see the specification of "Sonsky" paragraph [0008]) "...Doped region 128 ... is a heavily doped P++ region... Also, region 130...is a heavily doped N++ region (more heavily doped than region 116). Doped region 132... is a heavily doped N++ region .... Doped regions 130 and 116 correspond to a source region of device 100 and doped region 132 to a drain region of device 100... gate structure 110 corresponds to a primary gate of device 100 and gate structure 112 to a secondary gate of device 100. Well 18 extending under gate structure 110 also allows for an ultra-short channel region 137 between well 18 and source region 130/116 which preserves a good property of a logic transistor (e.g. good RF performance). Note that the channel length of device 100 depends on how far well 18 extends under gate structure 110 because the channel length is defined as the overlap of region 110 over well 16. The secondary gate (gate structure 112) which is formed over well 18 and spaced apart from gate structure 110 and spaced apart from drain region 132 can be used to help shape the electrical field...." (see the specification of "Sonsky" paragraph [0023] and FIG. 15 as shown below). The persons with ordinary skill in the art can well know that the forming of the ultra-short channel region 137 is fundamentally based on the P-N junction between the Well 18 (N-type) and the Well 16 (P-type) with different conductivity types. In the N-type MOSFET, the inversion layer of the channel region is formed on the surface of the P-type body region (i.e., Well 16). If the P-type Well 16 is replaced to an N-type well to form a structure taught by "Huang" "that includes well regions with the same electrical property (HVNW, Fig. 10 and 1J1J[0037]-[0039])" (cited by the Office Action in page 5), the P-type body region disappears, the source region (the doped regions 130 and 116) will not be able to form a proper junction with the replaced N-type well, the channel region (ultra-short channel region 137) cannot be formed, and the semiconductor device 100 of "Sonsky" combine the features taught by "Huang" would be fail. This may cause fails to accomplish the invention object, e.g. "for improved performance, such as in an RF application" (see the specification in paragraph [0024]), of "Sonsky". It is submitted that, the "well regions with the same electrical property (HVNW, Fig. 10 and 1J1J[0037]-[0039])" (cited by the Office Action in page 5) taught by "Huang", in some sot, teach away from "Sonsky".
Moreover, the applicant argues that “[t]he symmetric HVNMOS device taught by "Huang" "that includes well regions with the same electrical property (HVNW, Fig. 10 and 1J1J[0037]-[0039])" (cited by the Office Action in page 5) cannot properly referred to the claimed first/second well region with the same conductivity type as set forth in the amended independent claim 1. "Huang" explicitly suggest that "... HVNMOS...having a symmetric structure, wherein the HVNMOS device includes two HVNW regions and an HVPW region therebetween..." (see the specification of "Huang" in paragraph [0038] and FIG.10 …). Although "Huang" suggests that the HVNMOS device includes two symmetric HVNW regions with the same conductivity type, but the HVPW region disposed between these two HVNW regions is also critical for accomplish the electric function of the HVNMOS. The HVNMOS device taught by "Huang" does not merely teach two HVNW regions with the same conductivity type. The HVNMOS (FIG. 10) taught by "Huang" has HVNW regions and HVPW region with different conductivity types. The Examiners fail to express for what reason the persons with ordinary skill in the art can be motivated to form be the second well region (the P-type Well 16) of "Sonsky" with the same conductivity type, based on HVNMOS (FIG. 10) of "Huang". It is submitted that, in the case of the rejection, the Examiner use the applicant's teaching features as blueprints to hunt through the prior art and combine them in rendering the present invention obvious. The cited references are viewed with the benefit of hindsight vision afforded by the claimed invention during the Examination.
In view of the foregoing, the cited references "Sonsky" and "Huang" cannot establish a prima facie case of obviousness over the amended independent claim 1 of the present application. Therefore, the amended independent claim 1 is unobvious and patentable over the cited references "Sonsky" and "Huang"”. The examiner respectfully disagrees.
To begin with, with respect to the applicant’s argument that one of ordinary skill in the art would not combine Sonsky and Huang as “[i]t woud not be reasonable, possible and logical “to form the second well region of Sonsky with the same electrical property as that of the first well region”, as doing so would eliminate presence of a necessary p-n junction between n-type well and p-type well, and thus destroy device disclosed by Sonsky. It is noted that the combination of Sonsky and Huang does not rely on a simple substitution of one conductivity type well for another. Namely, contrary to the applicant’s suggestion, Huang is not relied upon for the teaching that one of the wells (Sonsky, e.g. p-type well 16, Fig. ) can be replaced with an opposite conductivity type (e.g. n-type) in order for both wells to be of the same conductivity type. Rather, Huang is relied upon for the totality of its disclosure. As discussed above in the rejection of claim 1, and also below, Sonsky discloses an asymmetric MOS device that includes a first well (16, Fig. 15) of a first conductivity type (¶[0008]) and a second well (18, Fig. 15) of a second conductivity type (¶[0008]). Contrary to the applicant’s argument, rather than changing conductivity of one of the two wells disclosed by Sonsky so that both first and second wells are of the same conductivity type, Huang is relied upon for the teaching that asymmetric MOS device, such as that disclosed by the Sonsky and Huang in Fig. 8A, and symmetric MOS device, such as that disclosed by Huang in Fig. 10 and claimed, are well-known alternative high-voltage MOS devices. Specifically, Huang teaches that symmetric MOS device requires two of the same conductivity type wells spaced apart by a region (well) of a different conductivity type. Thus, contrary to the applicant’s argument, substitution of the well structures used in the symmetric MOS device for the well structures used in the asymmetric MOS device, would not eliminate presence of the p-n junction between n-type and p-type regions, but would merely provide an alternative way of forming a MOS device. Accordingly, the combination of Sonsky with Huang is proper.
Furthermore, in response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). As discussed above, Huang teaches that asymmetric MOS device (Fig. 8A), such as that disclosed by Sonsky, that includes a first well (26, Fig. 8A and ¶[0024]) having a first conductivity type (¶[0024]) and a second well (28, Fig. 8A and ¶[0024]) having a second conductivity type (¶[0024]), different from the first conductivity type, and a symmetric MOS device (Fig. 10) that includes first well (HVNW, Fig. 10 and ¶[0038]) and second well (HVNW, Fig. 10 and ¶[0038]) having the same conductivity types with an third region (HVPW, Fig. 10 and ¶[0038]) of a different conductivity type from that of first and second well therebetween, are alternative structures that can be used when forming high-voltage metal-oxide-semiconductor (MOS) devices depending on specific design requirements (¶[0004]). The symmetric MOS device disclosed by Huang, that includes a well structure between the first and second well structure of the same conductivity, is the same structure as disclosed by the applicant. Specifically, Huang explicitly teaches that asymmetric MOS device, such as that disclosed by Sonsky and Huang in Fig. 8A, and symmetric MOS device, such as that disclosed by the applicant and Huang in Fig. 10, are well-known alternative high-voltage MOS devices. Combination of Sonsky and Huang does not merely rely on Huang for changing the conductivity type of one of the well regions disclosed by Sonsky to a different conductivity type. Rather, Huang is relied upon for showing that an asymmetric device can be replaced with a symmetric device, which would require for the two wells of different conductivity types (Huang, 26 and 28, Fig. 8A) to be replaced with two wells of the same conductivity type (Huang, HVNW, Fig. 10) with a region of different conductivity type (Huang, HVPW, Fig. 10) placed therebetween (which is the same structure as that disclosed by the applicant, which includes two wells (203 and 202, Fig. 2D) of the same conductivity type, with a region (201A, Fig. 2D) of a different conductivity type formed therebetween). Thus, contrary to the applicant’s argument, rather than relying on the applicant’s disclosure “to hunt through the prior art and combine them in rendering the present invention obvious”, the prior art itself provides a motivation for replacing the asymmetric MOS device structure disclosed by Sonsky and Huang in Fig. 8A ,with the symmetric MOS device disclosed by Huang in Fig. 10 and claimed by the applicant. Accordingly, the combination of Sonsky and Huang is considered proper.
Relevant Prior Art
The prior art of record and not relied upon is considered pertinent to applicant’s disclosure:
Chen et al. (US 20150236150) discloses in Fig. 1 and related text a dual gate MOS device in which first and second wells (102, 104, Fig. 1) are formed in a third well (i.e. deep well, 116 or 114, Fig. 1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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