DETAILED ACTION
This Office Action is in response to RCE filed August 19, 2025.
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 3 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention. Applicants originally disclosed in paragraph [0015] of current application that “The second region of the oxide semiconductor layer is amorphous or is formed of a mixture of amorphousness and microcrystals, where an amorphous region is dotted with microcrystals, or is formed of microcrystals”; in paragraph [0021] of current application that “The second region is amorphous or is formed of a mixture of amorphousness and microcrystals, where an amorphous region is dotted with microcrystals, or is formed of microcrystals”; in paragraph [0073] of current application that “The oxide semiconductor layer 103 is an amorphous layer having many dangling bonds at the stage where the oxide semiconductor layer 103 is formed”, that “Through a heating step for the dehydration or dehydrogenation, dangling bonds within a short distance are bonded to each other, so that the oxide semiconductor layer 103 can have an ordered amorphous structure”, that “As ordering proceeds, the oxide semiconductor layer 103 comes to be formed of a mixture of amorphousness and microcrystals, where an amorphous region is dotted with microcrystals, or be formed of a microcrystal group (emphasis added)”, and that “Here, a microcrystal is a so-called nanocrystal with a particle size of from 1 nm to 20 nm, which is smaller than that of a microcrystalline particle generally called a microcrystal”; and in paragraph [0074] of current application that “In the superficial portion of the oxide semiconductor layer 103, which is the crystal region 106, a microcrystalline layer in which microcrystals are c-axis-oriented in a direction perpendicular to a surface of the layer is preferably formed (emphasis added)”, and that “In that case, the long axis of the crystal is in the c-axis direction and the crystal in the short-axis direction is from 1 nm to 20 nm.” Therefore, Applicants did not originally disclose that “the oxide semiconductor layer includes a second region including a second crystal under the first region (emphasis added)” as recited on lines 9-10, where the second region includes nanocrystals with the particle size of 1 nm to 20 nm as recited on lines 11-12, because (a) Applicants did not originally disclose where the second region including the second crystal including the nanocrystals with a particle size of 1 nm to 20 nm recited on lines 11-12, (b) furthermore, Applicants did not originally disclose whether “an amorphous region” “dotted with microcrystals” mentioned in paragraph [0073] of current application is the same with or different from “the crystal region” mentioned in paragraph [0074] of current application, and (c) therefore, Applicants did not originally disclose a stacked crystalline structure with the first region including the first crystal that is c-axis-oriented disposed above the second crystal including the nanocrystals with the particle size of 1 nm to 20 nm since it appears that the claimed particle size is a particle size of the c-axis-oriented microcrystals disposed in the first region rather than a particle size of an unspecified crystal orientation under the first region.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim 3 is rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Kim et al. (“Effect of indium composition ratio on solution-processed nanocrystalline InGaZnO thin film transistors,” APPLIED PHYSICS LETTERS 94 (2009) 233501)
Kim et al. disclose a semiconductor device (Title) comprising: a transistor (InGaZnO thin film transistor) comprising an oxide semiconductor layer (InGaZnO) comprising a channel formation region, wherein the oxide semiconductor layer comprises an In-Ga-Zn-O-based oxide semiconductor, wherein the oxide semiconductor layer has a first region (arbitrary region of InGaZnO) in a superficial portion that includes a first crystal that is c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer, because (a) Kim et al. further disclose that “This obstructs c-axis growth of IGZO resulting in a decrease of the grain size” on lines 3-4 of the right column of page 233501-2, which suggests that c-axis growth of the (polycrystalline or nanocrystalline) InGaZnO crystals mentioned on lines 9-18 of the left column of page 233501-2 is obstructed such that the InGaZnO crystals have decreased grain size in the c-axis direction or the direction perpendicular to the surface of the oxide semiconductor layer while the InGaZnO crystals are depositing and growing along the c-axis direction, and (b) in addition, the “(000l) orientation of InGaO3(ZnO)2 by x-ray diffraction pattern” mentioned on lines 17-18 of the left column of page 233501-2 includes the (0001) orientation with l = 1, which is the claimed c-axis orientation, wherein the oxide semiconductor layer includes a second region (another arbitrary region of InGaZnO) including a second crystal under the first region, because (a) Applicants do not specifically claim what the first and second region each refers to, how thick each of the first and second region is, (b) also, the preposition “under” does not necessarily suggest “directly under”, and (c) therefore, the oxide semiconductor layer disclosed by Kim et al. can be arbitrarily divided using an imaginary line to come up with the claimed first and second region, and wherein the second region includes nanocrystals (nanocrystals of polycrystalline or nanocrystalline InGaZnO) with a particle size of from 1 nm to 20 nm (~ 14.7 nm or ~ 7.6 nm on lines 21-24 of the left column of page 233501-2).
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Park et al. (“Investigation on doping dependency of solution-processed Ga-doped ZnO thin film transistor,” APPLIED PHYSICS LETTERS 93, 083508 (2008)) in view of Kim et al. (“Effect of indium composition ratio on solution-processed nanocrystalline InGaZnO thin film transistors,” APPLIED PHYSICS LETTERS 94 (2009) 233501)
Park et al. disclose a semiconductor device (Fig. 1) comprising: a transistor comprising an oxide semiconductor layer (GZO) comprising a channel formation region (region of GZO overlapping with MoW in plan view), wherein the oxide semiconductor layer has a first region (topmost horizontal region between source/drain electrode of IZO) in a superficial portion that includes a first crystal that is c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer (lines 2-14 of the second full paragraph on right column of page 083508-1), wherein the oxide semiconductor layer includes a second region (arbitrary region of inclined sidewall region adjacent topmost horizontal region between source/drain electrode of IZO) including a second crystal under the first region, because the preposition “under” does not necessarily suggest “directly under”, and wherein the second region includes nanocrystals, because the second region is also a part of the GaZnO layer, with a particle size of from 1 nm or more and 20 nm or less, see the scale bar of 100 nm and compare some crystal sizes with respect to the scale bar of 100 nm in Figs. 3(b) and 3(c) of Park et al., because particle sizes of some of the crystals shown in Figs. 3(b) and 3(c) of Park et al. are within the claimed range since (i) Applicants do not specifically claim how the claimed particle size is measured, and (ii) therefore, as long as there are two crystals having a particle size in the claimed range from any perspective, the claim limitation of claim 3 would be met (also, Kim et al. disclose a particle size of ~ 14.7 nm or ~ 7.6 nm on lines 21-24 of the left column of page 233501-2).
Park et al. differ from the claimed invention by not showing that the oxide semiconductor layer comprises an In-Ga-Zn-O-based oxide semiconductor.
Kim et al. disclose a semiconductor device (Title) comprising: a transistor (InGaZnO thin film transistor) comprising an oxide semiconductor layer (InGaZnO) comprising a channel formation region, wherein the oxide semiconductor layer comprises an In-Ga-Zn-O-based oxide semiconductor, wherein the oxide semiconductor layer has a first region (arbitrary region of InGaZnO) in a superficial portion that includes a first crystal that is c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer, because (a) Kim et al. further disclose that “This obstructs c-axis growth of IGZO resulting in a decrease of the grain size” on lines 3-4 of the right column of page 233501-2, which suggests that c-axis growth of the (polycrystalline or nanocrystalline) InGaZnO crystals mentioned on lines 9-18 of the left column of page 233501-2 is obstructed such that the InGaZnO crystals have decreased grain size while the InGaZnO crystals grow along the c-axis, and (b) the “(000l) orientation of InGaO3(ZnO)2 by x-ray diffraction pattern” mentioned on lines 17-18 of the left column of page 233501-2 includes (0001) orientation, which is the claimed c-axis orientation, wherein the oxide semiconductor layer includes a second region (another arbitrary region of InGaZnO) including a second crystal under the first region, because Applicants do not specifically claim what the first region/superficial portion and the second region refer to, and wherein the second region includes nanocrystals (nanocrystals of polycrystalline or nanocrystalline InGaZnO) with a particle size of 1 nm to 20 nm (~ 14.7 nm or ~ 7.6 nm on lines 21-24 of the left column of page 233501-2).
Since both Park et al. and Kim et al. teach solution-processed oxide semiconductor channel layers having c-axis-oriented crystals, it would have been obvious to one of ordinary skill in the art at the time the invention was made that the oxide semiconductor layer disclosed by Park et al. can comprise an In-Ga-Zn-O-based oxide semiconductor as disclosed by Kim et al., because (a) an InGaZnO oxide semiconductor layer has been commonly employed as a channel layer of a thin film transistor due to its larger and wider range of bandgaps and lattice constants since it is a quaternary compound semiconductor, (b) therefore, an In-Ga-Zn-O-based oxide semiconductor can be employed in a wider range of applications than a tertiary compound semiconductor such as GaZnO disclosed by Park et al., (c) just as Park et al. disclose doping of ZnO with Ga to form a tertiary compound semiconductor of GaZnO, a quaternary compound semiconductor of InGaZnO can also be easily formed by additionally doping ZnO or GaZnO with In, and (d) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416.
Response to Arguments
Applicants’ arguments with respect to claim 3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants argue that “Regarding independent claim 3, this claim clarifies that the oxide semiconductor has a first region in a superficial portion that includes a first crystal that is c-axis oriented in a direction perpendicular to a surface of the oxide semiconductor layer, and includes a second region including a second crystal under the first region, wherein the second region includes nanocrystals with a particle size of 1 nm to 20 nm”, and that “These features are supported, for example, by at least Applicant's FIGS. 1A-1B, 27B and associated text” on page 4 of the REMARKS filed August 19, 2025. However, these arguments are not persuasive, because Applicants did not originally disclose a stacked structure of the first and second region with the second region including the claimed nanocrystals with the claimed particle size under the first region. In other words, Applicants did not originally disclose where exactly the nanocrystals with the claimed particle size are located, and it does not appear that Applicants measured the particle size of a plurality of nanocrystals along the vertical direction of the oxide semiconductor layer at multiple locations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yamaguchi et al. (US 8.748,878)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 February 5, 2026