DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I of Group I, claims 1-6, 11, 16, 17 and 21 in the reply filed on 2/11/26 is acknowledged. The traversal is on the ground(s) that the product as claimed cannot be made by another and materially different process and that no serious burden would be placed on the examiner to examine all claims to all inventions. This is not found persuasive because it has been shown that the product as claimed can be made by another and materially different process, see paper dated 12/22/25. Furthermore, as noted previously, should the product be deemed allowable, the process of making said product would be rejoined if the allowable subject matter is contained therein. As for the serious burden, the multitude of limitations pertaining to a plurality of inventions would absolutely burden the examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 16, 17 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sriram et al. (US 2019/0333767).
Regarding claim 1, Sriram discloses a transistor comprising:
a group III-Nitride channel layer (104, fig. 5 and paragraph 0072);
a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer comprising a higher bandgap than a bandgap of the group III- Nitride channel layer (106, fig. 5 and paragraph 0072);
a low resistance contact layer on the group III-Nitride barrier layer and/or on the group III-Nitride channel layer (150, fig. 5 and paragraph 0075);
a source electrically coupled to the group III-Nitride barrier layer (110, fig. 5 and paragraph 0073);
a drain electrically coupled to the group III-Nitride barrier layer (114, fig. 5 and paragraph 0073); and
a gate on the group III-Nitride barrier layer (112, fig. 5 and paragraph 0074),
wherein at least one of the drain and the source are arranged on the low resistance contact layer (110 on 150, fig. 5).
Regarding claim 2, Sriram further discloses wherein the low resistance contact layer comprises GaN (150, fig. 5 and paragraph 0076).
Regarding claim 3, Sriram further discloses wherein the low resistance contact layer comprises n-type GaN (paragraph 0076).
Regarding claim 4, Sriram further discloses wherein the low resistance contact layer (150, fig. 5) comprises a sputtered layer, a physical vapor deposited layer, a doped GaN film layer, and/or a n-type sputtered GaN layer (paragraph 0076).
Regarding claim 6, Sriram further discloses wherein the low resistance contact layer (150, fig. 5) comprises a sputtered layer, a layer formed by sputtering, a physical vapor deposited layer, a layer formed by physical vapor deposition, a doped GaN film layer, a n-type sputtered GaN layer, and/or a layer formed by sputtering n-type GaN (paragraphs 0072-0076).
Regarding claim 16, Sriram further discloses wherein the low resistance contact layer is configured to improve a performance of the transistor (paragraph 0067).
Regarding claim 17, Sriram further discloses wherein the low resistance contact layer is configured to improve a radiofrequency performance of the transistor (paragraph 0067).
Regarding claim 21, Sriram further discloses comprising a field plate (paragraph 0130).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Sriram et al. (US 2019/0333767).
Regarding claim 5, Sriram discloses the transistor of claim 1, as mentioned above. Sriram does not explicitly disclose wherein the low resistance contact layer comprises a n-type sputtered GaN layer. Sriram discloses layer 150 formed from an implantation process (paragraphs 0075-0077). However, a n-type sputtered GaN layer would be deemed as a known functional equivalent in the art of semiconductor manufacturing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Regarding claims 9 and 11, Sriram discloses the transistor of claim 1, as mentioned above. Sriram further discloses wherein the drain and/or source is arranged on the low resistance contact layer (paragraph 0077). Sriram does not explicitly disclose wherein there is one or more intervening layers therebetween. However, the use of an intervening layer would be deemed obvious to one of ordinary skill in the art at the time of filing since such was widely practiced at the time and the Examiner take official notice of such practice.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication US 2015/0295051 discloses a relevant hemt structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 5/16/26
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