Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding claims 7-8, 12-19 rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections from the prior office action. Hence, 35 U.S.C. 112(b) rejection is withdrawn.
Applicant's arguments filed on 04/13/2026 have been fully considered but they are not persuasive.
Regarding claims 1, 12 and 20, Liu teaches implanted/doped regions 110 formed below tapered trenches 106 by ion implantation. Liu further teaches that regions 110 act as trench extensions. Thus, Liu teaches the damaged trench-extension consists the tapered sidewalls.
Regarding claims 3, 4, 6, 7, and 9, Choi is not relied upon for the tapered sidewalls feature. Choi is relied upon to show that ion implantation forms a dislocation region.
Regarding claims 5, 11, and 14, Schmidt teaches liner 126 on trench sidewall and a bottom surface before trench fill. When applied to the Twynam/Liu structure, the liner is between the insulator material and the damaged region.
Hence, the prior art relied upon teach the disputed limitations, and the rejections are maintained for claims 1-20.
Claim Objections
Claims 4 and 10 are objected to because of the following informalities:
Claim 4 recites “…wherein the insulator material comprise tapered sidewalls”. It should be “…wherein the insulator material comprises tapered sidewalls”. Appropriate correction is required.
Claim 10 recites “…wherein the insulator material comprise straight vertical sidewalls”. It should be “…wherein the insulator material comprises straight vertical sidewalls”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 10, 12-13, 15-16, 18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Twynam (US 20200176594 A1) in view of Liu (US 20020037627 A1).
Re: Independent Claim 1 (Currently Amended), Twynam discloses a structure comprising:
a stack of semiconductor materials (Twynam, Figs 2A-2F, ¶ [0057] - [0064], epitaxial group III nitride based multilayer structure 33 that include a stack of epitaxial Group III nitride layers);
a semiconductor substrate under the stack of semiconductor materials (support substrate 30 having first surface 31 on which the multilayer Group III nitride structure 33 is grown);
a trench in the stack of semiconductor materials and filled with an insulator material (trench 39 formed in non-device region 42 is filled with insulation layer 51); and
a damaged region of the stack of semiconductor materials (implantation-formed charge mobility reduction regions 43 and 45, i.e., damaged region formed at least on the first surface 31 of substrate 30).
Twynam is silent regarding damaged region of the stack of semiconductor materials extending from at least a bottom of the insulator material to the semiconductor substrate, wherein the damaged region comprises tapered sidewalls.
However, Liu teaches, in Fig 3, ¶ [0025] and ¶ [0028], etching trenches 106 in a silicon substrate 102 and then performing ion implantation 108 to form implanted regions 110 that act as trench extensions, i.e., an electrically insulating region extending downward from the bottom surface of the trench, followed by filling the trenches with dielectric 112. Accordingly, implanted regions 110 is the claimed damaged region, and because 110 is the extension of the trench with tapered sidewalls as shown in Fig. 3, damage region 110 comprises tapered sidewalls.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Twynam's etched non-device region/trench by incorporating Liu's trench-bottom implantation approach so that Twynam's implantation-formed damaged region (charge mobility reduction region 43/45) is made to extend downward form at least the bottom of the trench/insulator fill region (51) into/through to the underlying semiconductor substrate in order to provide a shallow trench isolation structure which has greater depth, and therefore greater ability to perform its role as an electrical isolation structure (Liu, [0022]).
Re: Claim 2 (Original), Twynam and Liu disclose all the limitations of claim 1 on which this claim depends. Twynam further discloses,
wherein the stack of semiconductor materials comprises wide-bandgap semiconductor material (Twynam teaches, in ¶ [0059], the semiconductor stack 33 is a Group III nitride-based multilayer structure (33) (e.g., GaN/AlGaN-based epitaxial structure). Group III nitrides are wide-bandgap semiconductor materials).
Re: Claim 10 (Currently Amended), Twynam and Liu disclose all the limitations of claim 1 on which this claim depends. Twynam further discloses,
wherein the insulator material comprise straight vertical sidewalls (Twynam Fig. 2F, insulating material 51 comprise straight vertical sidewalls 46).
Re: Independent Claim 12 (Currently Amended), Twynam discloses a structure, comprising:
a wide-bandgap semiconductor layer of a semiconductor substrate (Twynam teaches, in Fig. 2F and ¶ [0059], support substrate 30 having a Group III nitride-based multilayer structure (33), and Group III nitrides are wide-bandgap semiconductor materials);
a device over the wide-bandgap semiconductor layer (Twynam, ¶ [0067], transistor device 54 (i.e., source electrode 55 gate electrode 56 and drain electrode 57) is formed on the upper surface 53 of each mesa 38 of the Group III nitride multilayer structure 33);
a trench in the wide-bandgap semiconductor layer which is filled with in insulator material surrounding the device (Twynam teaches forming a trench i.e., opening/non-device region 42 is formed in wide-bandgap semiconductor layer 33 and filled with insulator material 51); and
a damaged region of the wide-bandgap semiconductor layer extending from at least a bottom of the trench to the semiconductor substrate and surrounding the device in a plan view (damaged region 45 extending from at least bottom of opening 42 to the semiconductor substrate 30 and 45 surrounds device 54 in plan view).
Twynam is silent regarding wherein the damaged region comprises tapered sidewalls.
However, Liu teaches, in Fig 3, ¶ [0025] and ¶ [0028], etching trenches 106 in a silicon substrate 102 and then performing ion implantation 108 to form implanted regions 110 that act as trench extensions, i.e., an electrically insulating region extending downward from the bottom surface of the trench, followed by filling the trenches with dielectric 112. Accordingly, implanted regions 110 is the claimed damaged region, and because 110 is the extension of the trench with tapered sidewalls as shown in Fig. 3, damage region 110 comprises the tapered sidewalls.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Twynam's etched non-device region/trench by incorporating Liu's trench-bottom implantation approach so that Twynam's implantation-formed damaged region (charge mobility reduction region 43/45) is made to extend downward form at least the bottom of the trench/insulator fill region (51) into/through to the underlying semiconductor substrate and have a tapered sidewall profile in order to provide a shallow trench isolation structure which has greater depth, and therefore greater ability to perform its role as an electrical isolation structure (Liu, [0022]).
Re: Claim 13 (Original), Twynam and Liu disclose all the limitations of claim 12 on which this claim depends.
Liu further teaches wherein the trench comprises tapered sidewalls. (Liu teaches in Fig 3, the trench 106 has tapered sidewalls).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement tapered sidewalls teaching of Liu to the trench of Twynam in order facilitate dielectric fill and to provide better electrical isolation (Liu, ¶ [0038]).
Re: Claim 15 (Original), Twynam and Liu disclose all the limitations of claim 12 on which this claim depends. Twynam further discloses,
wherein the trench partially extends within the wide- bandgap semiconductor layer (Twynam teaches charge mobility reduction region (45) extends through the wide- bandgap semiconductor layer 33, thus teaching 45 obviously extends partially though the wide- bandgap semiconductor layer).
Re: Claim 16 (Currently Amended), Twynam and Liu disclose all the limitations of claim 12 on which this claim depends. Twynam further discloses,
wherein the damaged region extends into the semiconductor substrate and has a higher resistivity than the wide-bandgap semiconductor layer and the semiconductor substrate. (Twynam teaches, in Fig. 2E, forming the damaged region 43 which is a damaged region that extends into the semiconductor substrate. Twynam further teaches, in ¶ [0064], that the charge mobility reduction regions 43/45 are formed by implantation and may have polycrystalline structure or an amorphous or a high-defect density structure, and that the charge mobility reduction regions may consist of regions of high trap density that reduce the number of electrons or holes available for current conduction. Twynam further teaches that the resistance of the charge mobility reduction regions 43/45 is increased due to a reduction in the density of free electrons or holes, and that such regions prevent current flow in parasitic channels (see Twynam ¶ [0028]). Therefore, Twynam teaches that the implantation-damaged/high-defect-density region has a higher resistivity than the surrounding undamaged wide-bandgap semiconductor layer and substrate regions).
Re: Claim 18 (Original), Twynam and Liu disclose all the limitations of claim 12 on which this claim depends. Twynam further discloses,
wherein the damaged region extends from a top surface of the wide-bandgap semiconductor to a bottom surface of the wide-bandgap semiconductor (Twynam teaches charge mobility reduction region (45) extends entirely through the semiconductor stack 33 which is the wide-bandgap semiconductor).
Re: Independent Claim 20 (Currently Amended), Twynam discloses a method comprising:
forming a stack of semiconductor materials on a semiconductor substrate (Twynam teaches, in Figs 2A-2F and ¶ [0059], forming a Group III-nitride multilayer structure 33 (stack) on a support substrate 30 (with first surface 31));
forming a trench partially in the stack of semiconductor materials (Twynam teaches forming trench partially in the stack by patterning/etching the stack (removing regions 39) to form non-device regions 42 adjacent the mesa 38, i.e., a trench/open region in the stack);
filling the trench with insulator material (Twynam teaches, in Fig 2E, filling the non-device regions 42 with insulation layer 51).
Twynam is silent regarding,
damaging a region of the stack of semiconductor materials extending from at least a bottom of the trench to the semiconductor substrate, wherein the damaged region comprises tapered sidewalls.
However, Liu teaches, in Fig 3, ¶ [0025] and ¶ [0028], etching trenches 106 in a silicon substrate 102 and then performing ion implantation 108 to form implanted regions 110 that act as trench extensions, i.e., an electrically insulating region extending downward from the bottom surface of the trench, followed by filling the trenches with dielectric 112. Accordingly, implanted regions 110 is the claimed damaged region, and because 110 is the extension of the trench with tapered sidewalls as shown in Fig. 3, damage region 110 comprises tapered sidewalls.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Twynam's etched non-device region/trench by incorporating Liu's trench-bottom implantation approach so that Twynam's implantation-formed damaged region (charge mobility reduction region 43/45) is made to extend downward form at least the bottom of the trench/insulator fill region (51) into/through to the underlying semiconductor substrate in order to provide a shallow trench isolation structure which has greater depth, and therefore greater ability to perform its role as an electrical isolation structure (Liu, [0022]).
Regarding the limitation “the damaged region has a higher resistivity than the stack of semiconductor materials and the semiconductor substrate”, Twynam teaches, in ¶ [0064], that the charge mobility reduction regions 43/45 are formed by implantation and may have polycrystalline structure or an amorphous or a high-defect density structure, and that the charge mobility reduction regions may consist of regions of high trap density that reduce the number of electrons or holes available for current conduction. Twynam further teaches that the resistance of the charge mobility reduction regions 43/45 is increased due to a reduction in the density of free electrons or holes, and that such regions prevent current flow in parasitic channels (see Twynam ¶ [0028]). Therefore, Twynam teaches that the implantation-damaged/high-defect-density region has a higher resistivity than the surrounding undamaged stack of semiconductor materials and substrate regions.
Claims 3, 4, 6, 7, 9, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Twynam (US 20200176594 A1) in view of Liu (US 20020037627 A1) further in view of Choi (US 6258693 B1).
Re: Claim 3 (Currently Amended), Twynam and Liu disclose all the limitations of claim 2 on which this claim depends.
Twynam and Liu are both silent regarding,
wherein the damaged region comprises a high-density crystalline dislocation region of the stack of semiconductor materials.
However, Choi teaches wherein the damaged region comprises a high-density crystalline dislocation region of the stack of semiconductor materials (Although Twynam, in ¶ [0062]-[0064], teaches damaged region in the stack, namely forming a parasitic channel suppression region /charge mobility reduction region 45 on side faces 46 of the mesa 38, where region 45 is formed by implantation and may have a polycrystalline /amorphous/high-defect density structure (i.e., implantation-damaged crystalline structure), to the extent Twynam does not expressly label the high-defect density damaged region as a "dislocation region". Choi teaches, in Fig 2C and column 6 lines 45-68 to column 7 lines 1-15, forming a dislocation region 56 in a semiconductor substrate by ion implantation (e.g., oxygen ions 55 implanted through an opening), and explains that the dislocation region 56 is distinct from non-ion damaged semiconductor regions 57. Choi further teaches implanting ions in a gradient from the surface 58 downward through the dislocation region 56, evidencing a region characterized by a high concentration of implantation-induced dislocations relative to adjacent undamaged regions).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement/understand Twynam's implantation-formed damaged region in the epitaxial Group III nitride stack ( e.g., regions 43/45 formed by implantation and described as locally disrupting crystallinity/high-defect density) as comprising a dislocation-rich damaged crystalline region, as taught by Choi's express disclosure that ion implantation forms a "dislocated region" in the implanted semiconductor in order to extend the scalability of isolation techniques (Choi, column 2, lines 37-40).
Regarding the limitation “the damaged region has a higher resistivity than the wide-bandgap semiconductor material and the semiconductor substrate”, Twynam teaches, in ¶ [0064], that the charge mobility reduction regions 43/45 are formed by implantation and may have polycrystalline structure or an amorphous or a high-defect density structure, and that the charge mobility reduction regions may consist of regions of high trap density that reduce the number of electrons or holes available for current conduction. Twynam further teaches that the resistance of the charge mobility reduction regions 43/45 is increased due to a reduction in the density of free electrons or holes, and that such regions prevent current flow in parasitic channels (see Twynam ¶ [0028]). Therefore, Twynam teaches that the implantation-damaged/high-defect-density region has a higher resistivity than the surrounding undamaged wide-bandgap semiconductor material and substrate regions.
Re: Claim 4 (Currently Amended), Twynam, Liu and Choi disclose all the limitations of claim 3 on which this claim depends.
Liu further teaches, wherein the insulator material comprise tapered sidewalls (Liu teaches in Fig 3, the trench 106 has tapered sidewalls, such that the filled insulator in the trench (dielectric 112) correspondingly comprises tapered sidewalls).
Re: Claim 6 (Original), Twynam, Liu and Choi disclose all the limitations of claim 3 on which this claim depends.
Twynam and Liu further teach,
wherein the damaged region extends entirely through the semiconductor stack of material and into the semiconductor substrate (Twynam teaches charge mobility reduction region (45) extends entirely through the semiconductor stack 33. Liu further teaches extending damaged region (ion implanted region 110) into semiconductor substrate 102).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Liu's implantation approach that forms a region extending into the substrate to Twynam's implantation- based parasitic channel suppression structure in order to improve electrical isolation (Liu, ¶ [0022]).
Re: Claim 7 (Currently Amended), Twynam, Liu and Choi disclose all the limitations of claim 3 on which this claim depends.
Twynam further teaches,
wherein the damaged region surrounds an active device in a plan view (Twynam, Fig 2F, damaged region 45 surrounds active device (i.e., transistor including source electrode 55, a gate electrode 56 and a drain electrode 57) in a plan view).
Re: Claim 9 (Original), Twynam, Liu and Choi disclose all the limitations of claim 3 on which this claim depends.
Twynam and Liu further teach,
wherein the damaged region extends partially through the semiconductor stack of material and into the semiconductor substrate (Twynam teaches charge mobility reduction region (45) extends through the semiconductor stack 33, thus teaching 45 obviously extends partially through the semiconductor stack. Liu further teaches extending damaged region (ion implanted region 110) into semiconductor substrate 102).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Liu's implantation approach that forms a region extending into the substrate to Twynam's implantation- based parasitic channel suppression structure in order to improve electrical isolation (Liu, ¶ [0022]).
Re: Claim 17 (Original), Twynam and Liu disclose all the limitations of claim 12 on which this claim depends.
Twynam and Liu are silent regarding,
wherein the damaged region comprises a high-density crystalline dislocation region.
However, Choi teaches
wherein the damaged region comprises a high-density crystalline dislocation region (Although Twynam, in ¶ [0062] - [0064], teaches damaged region in the stack, namely forming a parasitic channel suppression region /charge mobility reduction region 43 lateral to side faces 46 of the mesa 38, where region 43 is formed by implantation and may have a polycrystalline /amorphous/high-defect density structure (i.e., implantation-damaged crystalline structure), to the extent Twynam does not expressly label the high-defect density damaged region as a "dislocation region". Choi teaches, in Fig 2C and column 6 lines 45-68 to column 6 lines 1-15, forming a dislocation region 56 in a semiconductor substrate by ion implantation (e.g., oxygen ions 55 implanted through an opening), and explains that the dislocation region 56 is distinct from non-ion damaged semiconductor regions 57. Choi further teaches implanting ions in a gradient from the surface 58 downward through the dislocation region 56, evidencing a region characterized by a high concentration of implantation-induced dislocations relative to adjacent undamaged regions).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement/understand Twynam's implantation-formed damaged region in the epitaxial Group III nitride stack ( e.g., regions 43/45 formed by implantation and described as locally disrupting crystallinity/high-defect density) as comprising a dislocation-rich damaged crystalline region, as taught by Choi's express disclosure that ion implantation forms a "dislocated region" in the implanted semiconductor in order to extend the scalability of isolation techniques (Choi, column 2, lines 37-40).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Twynam (US 20200176594 A1) in view of Liu (US 20020037627 A1) further in view of Choi (US 6258693 B1) and further in view of Schmidt (US 20180108675 A1).
Re: Claim 5 (Currently Amended), Twynam, Liu and Choi disclose all the limitations of claim 4 on which this claim depends.
Twynam, Liu and Choi are silent regarding
wherein the tapered sidewalls and a bottom surface of the insulator material comprise a liner material between the insulator material and the damaged region.
However, Schmidt teaches
wherein the tapered sidewalls and a bottom surface of the insulator material comprise a liner material between the insulator material and the damaged region (Schmidt, Fig. 8B, trench 141 with tapered sidewalls and bottom surface comprise liner 126, where the liner is disposed between the trench-fill insulating material and the surrounding semiconductor material at the sidewalls and bottom of the trench.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Schmidt's liner (thermal oxide 126) along the tapered sidewalls and bottom surface of the trench before filling the trench with insulator material. Such a modification would have predictably placed the liner material between the insulator material and the surrounding/underlying implanted damaged region, including the damaged trench-extension region taught by Liu, and would have been made to improve dielectric isolation and reduce undesired leakage current (Schmidt, ¶ [0060]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Twynam (US 20200176594 A1) in view of Liu (US 20020037627 A1) further in view of Choi (US 6258693 B1) and further in view of Williams (US 20070278612 A1).
Re: Claim 8 (Currently Amended), Twynam, Liu and Choi disclose all the limitations of claim 7 on which this claim depends.
Twynam, Liu and Choi are silent regarding,
wherein the damaged region comprises several damaged regions at least one of which surrounds multiple active devices in a plan view.
However, Williams teaches wherein the damaged region comprises several damaged regions at least one of which surrounds multiple active devices in a plan view (Although Twynam teaches forming multiple implantation-damaged regions (43/45), including regions repeated around multiple mesa/devices, Twynam is silent regarding damaged regions surrounding multiple active devices. Williams teaches, in ¶¶ [0043]-[0044], configuring isolation so that trenches and doped sidewall regions are formed in an annular/circumscribing shape that encloses an isolation pocket of the substrate, and further etches that shallow dielectric-filled trenches may be formed within the same pocket to provide surface isolation among devices in that pocket, which evidences that multiple devices may be contained within a single pocket collectively surrounded by one annular isolation structure. For example, trenches 625A-625 circumscribe pockets 626A/626B and optional trenches 624A/624B provide isolation between devices within a given pocket).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Twynam's damaged-region isolation layout so that at least one of Twynam's implantation-damaged regions is arranged in the annular configuration taught by Williams to surround a group of active devices, in order to increase packing density of the semiconductor devices and conserve valuable real estate on the surface of the semiconductor chip (Williams, ¶ [0046]).
Claim 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Twynam (US 20200176594 A1) in view of Liu (US 20020037627 A1) further in view of Schmidt (US 20180108675 A1).
Re: Claim 11 (Currently Amended), Twynam and Liu disclose all the limitations of claim 10 on which this claim depends.
Twynam and Liu are silent regarding,
wherein the straight vertical sidewalls and a bottom surface of the insulator material are lined with a liner material between the insulator material and the damaged region.
However, Schmidt teaches
wherein the straight vertical sidewalls and a bottom surface of the insulator material are lined with a liner material between the insulator material and the damaged region (Schmidt, Fig. 8B, trench 141 with sidewalls and bottom surface comprise liner 126, where the liner is disposed between the trench-fill insulating material and the surrounding semiconductor material at the sidewalls and bottom of the trench.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the trench isolation structure of Ywynam, as modified by Liu, to include Schmidt's liner (thermal oxide 126) along the straight vertical sidewalls and bottom surface of the trench before filling the trench with insulator material. Such a modification would have predictably placed the liner material between the insulator material and the surrounding/underlying implanted damaged region, including the damaged trench-extension region taught by Liu, and would have been made to improve dielectric isolation and reduce undesired leakage current (Schmidt, ¶ [0060]).
Re: Claim 14 (Currently Amended), Twynam and Liu disclose all the limitations of claim 12 on which this claim depends.
Twynam and Liu are silent regarding,
wherein the trench is lined with an insulator liner between the damaged region and the insulator material.
However, Schmidt teaches
wherein the trench is lined with an insulator liner between the damaged region and the insulator material (Schmidt, Fig. 8B, trench 141 with tapered sidewalls and bottom surface comprise liner 126, where the liner is disposed between the trench-fill insulating material and the surrounding semiconductor material at the sidewalls and bottom of the trench.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include Schmidt's liner (thermal oxide 126) along the tapered sidewalls and bottom surface of the trench before filling the trench with insulator material. Such a modification would have predictably placed the liner material between the insulator material and the surrounding/underlying implanted damaged region, including the damaged trench-extension region taught by Liu, and would have been made to improve dielectric isolation and reduce undesired leakage current (Schmidt, ¶ [0060]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Twynam (US 20200176594 A1) in view of Liu (US 20020037627 A1) further in view of Williams (US 20070278612 A1).
Re: Claim 19 (Currently Amended), Twynam and Liu disclose all the limitations of claim 12 on which this claim depends.
Twynam and Liu are silent regarding,
wherein the damaged region comprises several damaged regions each of which surround a single device in a plan view and one of which surrounds multiple devices in the plan view.
However, Williams teaches
wherein the damaged region comprises several damaged regions each of which surround a single device in a plan view and one of which surrounds multiple devices in the plan view (Although Twynam teaches forming multiple implantation-damaged regions (43/45), including regions repeated around multiple mesa/devices, Twynam is silent regarding damaged regions surrounding multiple active devices. Williams teaches, in ¶¶ [0043] - [0044], configuring isolation so that trenches and doped sidewall regions are formed in an annular/circumscribing shape that encloses an isolation pocket of the substrate, and further etches that shallow dielectric-filled trenches may be formed within the same pocket to provide surface isolation among devices in that pocket, which evidences that multiple devices may be contained within a single pocket collectively surrounded by one annular isolation structure. For example, trenches 625A-625 circumscribe pockets 626A/626B and optional trenches 624A/624B provide isolation between devices within a given pocket).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Twynam's damaged-region isolation layout so that at least one of Twynam's implantation-damaged regions is arranged in the annular configuration taught by Williams to surround a group of active devices, in order to increase packing density of the semiconductor devices and conserve valuable real estate on the surface of the semiconductor chip (Williams, ¶ [0046]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 9:30am-6pm.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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