DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20190131242 A1) and Chang et al. (US 20230096703 A1).
Regarding claim 1, Lee et al. teaches a semiconductor structure, comprising;
a first substrate having a first side and a second side opposite to the first side [as seen in attached Fig. 9, ¶ 0008], wherein the first side includes a recess recessed from the first side to form a recessed surface [as seen in attached Fig. 9, ¶ 0008], wherein the first substrate further comprises a substrate conductive pad (122P) formed on the second side of the first substrate and a first substrate conductive line (112) formed on the recessed surface of the recess [as seen in attached Fig. 9, ¶ 0066];
a first semiconductor die (121) arranged in the recess [as seen in attached Fig. 9, ¶ 0008],
a second semiconductor die (122 or 123) electrically bonded to the second side of the first substrate via the substrate conductive pad [as seen in attached Fig. 9, ¶ 0066];
a second substrate electrically bonded to the first side of the first substrate [as seen in attached Fig. 9, ¶ 0009];
a plurality of conductive vias (143) positioned along the second substrate and extending through the second substrate [as seen in attached Fig. 9, ¶ 0068]; and
a plurality of conductive lines positioned on the second substrate and electrically coupled to the conductive vias respectively [as seen in attached Fig. 9, ¶ 0068];
wherein the first semiconductor die and the second semiconductor die are electrically coupled to the second substrate via the conductive lines respectively [as seen in attached Fig. 9, ¶¶ 0081 and 0068].
Lee et al. doesn’t teach the first semiconductor die in the recess wherein the first semiconductor dies has a first side electrically coupled to the first substrate conductive line and a second side opposite to the first side, wherein the second side of the first semiconductor die is free of conductive bonding.
Chang et al. teaches the first semiconductor die (420) wherein the first semiconductor dies has a first side electrically coupled to the first substrate conductive line [¶ 0030] and a second side opposite to the first side, wherein the second side of the first semiconductor die is free of conductive bonding [Fig. 3, ¶ 0031].
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to combine Lee et al. with Chang et al. to have a first die arranged in a recess with one side coupled to a conductive line and the second side opposite to the first side free of conductive bonding. Having one that is attached with conductive pads would allow for establishing a connection to active and passive devices and having one side free from conductive bonding would allow for a closer molding and insulation that allows for a more specified connection that minimizes the chance of leakage. A person with ordinary skill in the art would combine the structure and connection of the first semiconductor die in the recess as shown by Lee et al. because it would allow for a compact packaging that would increase efficiency.
PNG
media_image1.png
760
813
media_image1.png
Greyscale
PNG
media_image2.png
374
601
media_image2.png
Greyscale
Regarding claim 14, Lee et al. teaches a semiconductor structure, comprising:
a first substrate [as seen in attached Fig. 9] including a horizontal portion [as seen in attached Fig. 9] and a protrusion portion [as seen in attached Fig. 9, shown with the recess, the substrate protrudes on the sides of the recess] extending on a peripheral region of the horizontal portion;
a first semiconductor die (122) having a first side bonded to a first side of the horizontal portion [as seen in attached Fig. 9, ¶0008];
a second semiconductor die [121 Fig. 9, ¶ 0008] bonded to a second side of the horizontal portion and laterally surrounded by the protrusion portion [as seen in attached Fig. 9, ¶ 0008];
a second substrate electrically bonded to the protrusion portion of the first substrate [as seen in attached Fig. 9, ¶ 0008];
a passivation layer (151) positioned on the second substrate [as seen in attached Fig. 9, ¶ 0008]; and
a barrier layer (160) positioned on the second substrate and in the passivation layer (151) [as seen in attached Fig. 9, ¶¶ 0067 and 0090, seen as underbump metal layer in Lee et al. it provides the same function for better connection reliability].
Lee et al. doesn’t teach the first semiconductor die having an opposed second side being free of conductive bonding.
Chang et al. teaches the first semiconductor die having an opposed second side being free of conductive bonding [Fig. 3, ¶ 0031].
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to combine the structure of Chang et al. into Lee et al. because both structures disclose stacked semiconductor packaging and including the first semiconductor die having an opposing second side to the first side which is free from conductive bonding would allow for further targeted signaling which would improve efficiency and stability.
Regarding claim 15, Lee et al. in further view of Chang et al. teaches the semiconductor structure of claim 14, wherein the passivation layer (151) define a plurality of openings disposed along the passivation layer to expose a portion of the second substrate [as seen in attached Fig. 9, ¶ 0090, Lee et al.].
Regarding claim 16, Lee et al. in further view of Chang et al. teaches the semiconductor structure of claim 15, wherein the barrier layer (160) is positioned in the openings [as seen in attached Fig. 9, ¶ 0092].
Claims 2-5 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in further view of Chang et al. as applied to claim 1 above, and further in view of Noda et al. (Pub No. US 20180286782 A1).
Regarding claim 2, Lee et al. in further view of Chang et al. teaches the structure of claim 1 wherein each of the conductive vias (143) comprises a filler layer positioned along the second substrate and extending through the second substrate [as seen in attached Fig. 9, ¶¶ 0085 and 0089, Lee et al.].
Lee et al. doesn’t teach a conductive via with a filler layer that has two isolation layers positioned on two sides of the filler layer, wherein the two isolation layers are formed of silicon oxide, silicon nitride, silicon oxynitride, tetra- ethyl ortho-silicate, or parylene, epoxy, poly(p-xylene).
Noda et al. teaches a filler layer positioned along the second substrate and extending through the second substrate [Fig. 1, ¶0026]; and two isolation layers positioned on two sides of the filler layer, wherein the two isolation layers (17) are formed of silicon oxide, silicon nitride, silicon oxynitride, tetra- ethyl ortho-silicate, or parylene, epoxy, poly(p-xylene) [Fig. 1, ¶0026 (discloses silicon oxide and silicon nitride)].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement two isolation layers formed on the two sides of the filler layer with the specified materials in Lee et al., as required by the claims, because the isolation layers are implemented to prevent a short circuit between the through via and substrate as shown in Noda et al.
Regarding claim 3, the combination of Lee et al. in view of Chang et al. and Noda et al. teaches the semiconductor structure of claim 2, wherein one of the conductive vias further comprises a seed layer [142 Fig. 1, ¶0022, Noda et al.] positioned between the two isolation layers [17, Noda et al.] and the filler layer [183, Noda et al.] and between the filler layer and the corresponding conductive line positioned on the second substrate [142 Fig. 1, ¶¶0022-0025, Noda et al.].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement a seed layer in Lee et al. as the inclusion of a seed layer ensures vias are completely filled without any voids which can be hard in deep and narrow vias without a seed layer as taught by Noda et al. The seed layer also helps with the conductivity and adhesion as voids are less likely to occur.
Regarding claim 4, Lee et al. in view of Chang et al. and Noda et al. teaches the structure of claim 3 wherein one of the conductive vias further comprises an adhesive layer [181 Fig. 1, ¶¶0022-0025, marked as barrier metal layer, has same composition and behavior, Noda et al.] positioned between the seed layer (182) and the two isolation layers (10a) and between the seed layer [Fig. 1, ¶¶0022-0025, Noda et al.] and the corresponding conductive line on the second substrate, wherein the adhesive layer is formed of titanium, tantalum, titanium tungsten, or manganese nitride [181 Fig. 1, ¶¶0022-0025, mentions titanium and tantalum, Noda et al.].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement an adhesion layer in Lee et al. as the inclusion of an adhesive layer would help with bonding and prevent the copper of the via from peeling. It can also be used as a barrier layer as well to hinder unwanted diffusion of current.
Regarding claim 5, Lee et al. in further view of Chang et al. and Noda et al. teaches the semiconductor structure of claim 4, wherein one of the conductive vias further comprises a barrier layer (720, Chang et al.) positioned between the adhesive layer (770, Chang et al., has same material and function as the claimed adhesive layer) and the two isolation layers (17, Noda et al.) and between the adhesive layer and the corresponding conductive line on the second substrate, wherein the barrier layer is formed of tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or tantalum nitride/tantalum bilayer [¶¶ 0045 and 0041, titanium, titanium nitride, tantalum, tantalum nitride, Chang et al.].
It would have been obvious to a person with ordinary skill in the art to combine the art of Lee et al., Chang et al., and Noda et al. before the effective filing to form a barrier layer between an adhesive layer and an isolation layer as Lee et al. discloses conductive vias that would benefit from the structure of conductive vias that are brought in by Chang et al. and Noda et al. to increase the efficiency of the conductive via while minimizing leakage.
Regarding claim 7, Lee et al. in further view of Chang et al. and Noda et al. teaches the semiconductor structure of claim 5, wherein the two isolation layers have a thickness between about 1 μm and about 5 μm [¶ 0019, Noda et al., protective film that is the same material as the claimed isolation layers, thickness is seen to be less than 50 μm].
Regarding claim 8, Lee et al. in further view of Chang et al. and Noda et al. teaches the semiconductor structure of claim 7, wherein the seed layer is formed of copper or ruthenium [790 Fig. 5H, ¶ 0049, Chang et al., copper].
Regarding claim 9, Lee et al. in further view of Chang et al. and Noda et al. teaches the semiconductor structure of claim 8, wherein the filler layer is copper [830 Fig. 5G, ¶ 0054, Chang et al., conductive traces seen as filler layer in the claimed invention].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Chang et al. and Noda et al. as applied to claim 4, and further in view Moon (US 7229918 B2).
Regarding claim 6, Lee et al. in further view of Chang et al. and Noda et al. teaches the semiconductor structure of claim 5.
Lee et al. in further view of Chang et al. and Noda et al. doesn’t teach the thickness of the isolation layer.
Moon teaches wherein the two isolation layers have a thickness between about 50 nm and about 200 nm [104 Col. 3 Lines 47-Col. 4 Lines 6, the same material as disclosed as the claimed isolation layer and has a thickness about 500 nm or less].
It would have been obvious to a person with ordinary skill in the art to combine the teachings of Moon into Lee et al. in further view of Change et al. and Noda et al. to have a thickness for the two isolation layers between about 50 nm and about 200 nm as it would be seen as ideal for the semiconductor structure and to maintain a small structure.
Claim(s) 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Chang et al. and further in view of Tsuji et al. (Pub No. US 5930603).
Regarding claim 10, Lee et al. in view of Chang et al. teaches the semiconductor structure of claim 1, further comprises a molding material [132/131 Fig. 9, ¶ 0057, Lee et al.] and the second side of the first semiconductor die is entirely covered by the molding material [¶ 0033, Chang et al. teaches the die may be encapsulated in the encapsulant]
Lee et al. in view of Chang et al. doesn’t teach the molding material encapsulating the first substrate, the second substrate, the first semiconductor die, and the second semiconductor die.
Tsuji et al. teaches a molding material encapsulating [5, Fig. 10] the first substrate, the second substrate, the first semiconductor die, and the second semiconductor die [Fig. 10, Column 1, line 55, sealing resin].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement a molding material encapsulating the first substrate, second substrate, first semiconductor die, and second semiconductor die to Lee et al. in view of Chang et al. as it would give more security and stability to the semiconductor and protect the embodiments of the device from foreign particulates such as water as taught by Tsuji et al.
Regarding claim 11, Lee et al. in view of Chang et al. and Tsuji et al. teaches the semiconductor structure of claim 10, wherein the molding material includes epoxy resin, PI, BCB, PBO, or PEEK [¶ 0084, Lee et al., specifies epoxy resin but doesn’t limit to listed materials], wherein the first substrate (as seen in attached Fig. 3) further comprises a second substrate conductive line extended from the inner surface of the recess [connection from second substrate to the second semiconductor die is seen through conductive lines and materials having the same structure as claimed, Chang et al.] to the second side of the first substrate to electrically couple to the first semiconductor die and the second semiconductor die [as seen in attached Fig. 3, ¶¶ 0032-0034, Chang et al., conductive layers forming the connection].
A person with ordinary skill in the art would be able to combine Lee et al. in view of Chang et al. and Tsuji et al. to create the claimed invention before the effective filing date as the arts show conductive features for semiconductor packaging and the addition of conduction lines from the second substrate to connect the first and second dies would allow for a more secure conduction that would help with increasing efficiency and stability.
Regarding claim 12, Lee et al. in view of Chang et al. and Tsuji et al. teaches the semiconductor structure of claim 11, further comprises a plurality of connectors [170 Fig. 9, ¶0067, shown as electric connection structures, Lee et al.], wherein each of the connectors is positioned on the corresponding conductive lines [142 Fig. 9, ¶¶0067 and 0068, conductive lines seen as redistribution layers, Lee et al.], and a conductive wire extended out of the first substrate to electrically couple between the first substrate (10, Tsuji et al.) and the second semiconductor die (15, Tsuji et al.), wherein the conductive wire (16, Tsuji et al.) is encapsulated within the molding material (5, Tsuji et al.) [Fig. 10, Col. 10 Lines 51-60, Tsuji et al., the conductive wire connects the first substrate with a semiconductor die and the whole system is encapsulated within a molding material].
A person with ordinary skill in the art would have been able to create the claimed invention before the effective filing date as Lee et al. teaches the plurality of connectors and Tsuji teaches a conductive wire connecting a substrate with a semiconductor die. Including teachings of Tsuji into Lee et al. would have been within the purview of a person with ordinary skill in the art as implementing the conductive wire connection helps with the stability and efficiency of semiconductor packaging.
Regarding claim 13, Lee et al. further in view of Chang et al. and Tsuji et al. teaches the structure of claim 12 and further teaches the plurality of connectors is formed of Sn, Pb, Ni, Au, Ag, Cu, Bi, or combinations thereof [¶0093, discloses Sn and Cu and mentions the structure not being limited to the two, Lee et al.].
Claim 17-20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Chang et al. as applied to claim 16 above.
Regarding claim 17, Lee et al. in view of Chang et al. discloses the structure described in claim 16.
Lee et al. in view of Chang et al. doesn’t teach the thickness of the passivation layer being greater than the thickness of the barrier layer.
One of ordinary skill in the art would have been led to the recited passivation thickness and barrier layer thickness through routine experimentation to achieve a desired packaging structure.
In addition, the selection of passivation layer thickness and barrier layer thickness, it's obvious because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also in re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996)(claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also in re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and in re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Note that the specification contains no disclosure of either the critical nature of the passivation layer thickness and barrier layer thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen passivation layer thickness and barrier layer thickness or upon another variable recited in a claim, the Applicant must show that the chosen passivation thickness and barrier layer thickness is critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 18, Lee et al. in view of Chang et al. teaches the structure described in claim 17 and the structure further comprising a plurality of connectors positioned on the barrier layer [as seen in attached Fig. 9, ¶0092, Lee et al.].
Regarding claim 19, Lee et al. in view of Chang et al. teaches the structure described in claim 18 and wherein the structure has a first portion of the connector is extending to the passivation layer, completely filled the opening, and disposed on the barrier layer [as seen in attached Fig. 9, ¶0092, Lee et al.].
Regarding claim 20, Lee et al. in view of Chang et al. teaches structure described in claim 18 and wherein a second portion of the connector is protruding from a plane coplanar with the top surface of the passivation layer and disposed on the first portion of the connector [as seen in attached Fig. 9, ¶0092, Lee et al.].
Response to Arguments
Applicant's arguments filed 02/12/2026 have been fully considered but they are not persuasive. With regards to the amendments made to claims 1 and 14-16, Lee et al. was no longer applicable as a 102(a)(1) rejection. Chang et al. was brought in to reject the amended claims in conjunction with Lee et al. as a 103 rejection. The arguments made by applicant were in regards to Lee et al. as a 102 rejection and are seen not persuasive as the rejection parameters have changed and the art which rejected the claims has changed as well.
With regards to Lee et al., Noda et al., Shih et al., nor Tsuji et al. teaching a first semiconductor die disposed in the recess of the first substrate to electrically couple the recess surface of the recess with a first side of the first semiconductor die while opposed second side of the first semiconductor is die free of conductive bonding, Chang et al. is brought in and anticipates this.
Regarding claim 10, the argument is not seen as persuasive as Tsuji et al. teaches the whole semiconductor substrates and dies being encapsulated with a molding material and Chang et al. is further brought in to emphasizes the first semiconductor die is entirely covered (encapsulated) by the molding material.
Regarding claim 11, the argument is not seen as persuasive as Chang et al. teaches the amened claim as presented above.
Regarding claim 12, the argument is not seen as persuasive as Tsuji et al. teaches the amended claim as presented above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOOR MOHAMMAD ISMAIL TAHIR whose telephone number is (571)272-6166. The examiner can normally be reached Monday Friday, 8 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NOOR MOHAMMAD ISMAIL TAHIR/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893