DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/25/2024 and 01/02/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the " average gap between adjacent capacitors is in a range of 12 nm to 20 nm " and " the wordlines having a pitch equal to less than 0.6 x a bitline pitch " must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, 7, 9, 11, 12, 14, 15, and 19 are rejected under 35 U.S.C. 102 as being anticipated by Kim et al. ( US 2022/0115376 A1; hereinafter Kim )
Regarding claim 1, Kim teaches a hexagonal cell layout for a DRAM device ( Fig. 1A: HS1 ), the hexagonal cell layout comprising: a first placement layout comprising a plurality of first capacitor holes ( Fig. 1A #120 ) arranged in a center packed hexagonal pattern ( as shown in Fig. 1A ), each of the first capacitor holes having a length along a z-axis ( as shown in Fig. 1A ) and a generally round cross-section in an x-y plane ( Fig. 1A: D1 ); and a second placement layout overlapping the first placement layout ( Fig. 1A #130 ), the second placement layout comprising a plurality of second capacitor holes ( [0035] Therefore, as illustrated in FIG. 1A, upper surfaces of the plurality of lower electrodes 120 may be exposed through the support 130 ) arranged in a second center packed hexagonal pattern ( Fig. 1A: HS2 ) interlaced with and offset by half a word line pitch and half a bit line pitch from the plurality of first capacitor holes to form the hexagonal cell layout ( as shown in Fig. 1A ), wherein each of the second capacitor holes have a length along the z-axis ( as shown in Fig. 1A ) and a generally round cross-section ( Fig. 1A: D2 ) with three arc shaped cutouts in the x-y plane ( [0019] Referring to FIGS. 1A, 1B, 1C and 1D, the semiconductor device 100 including a plurality of lower electrodes 120 arranged on the semiconductor substrate 110 in a honeycomb structure and a support 130 having a plurality of open areas OP is illustrated ) to fit between each of the plurality of first capacitor holes ( Fig. 1A #120).
Regarding claim 2, Kim teaches a DRAM device comprising: a plurality of first capacitors ( Fig. 1A: #120 ) arranged in a center packed hexagonal pattern ( Fig. 1A: HS1 ), each of the first capacitors having a length along a z-axis ( as shown in Fig. 1A ) and a generally round cross-section in an x-y plane ( Fig. 1A: D1 ); a plurality of second capacitors ( [0035] Therefore, as illustrated in FIG. 1A, upper surfaces of the plurality of lower electrodes 120 may be exposed through the support 130 ) arranged in a second center packed hexagonal pattern ( Fig. 1A : HS2 ) interlaced with and offset by half a word line pitch and half a bit line pitch from the plurality of first capacitors ( as shown in Fig. 1A, the OP areas from #130 are interlaced with the #120 areas) so that an overall hexagonal array of alternating first capacitors and second capacitors is formed ( as discussed above), each of the second capacitors having a length along the z-axis ( as shown in Fig. 1A ) and a generally round cross- section ( Fig. 1A: D2) with three arc shaped cutouts in the x-y plane ( [0019] Referring to FIGS. 1A, 1B, 1C and 1D, the semiconductor device 100 including a plurality of lower electrodes 120 arranged on the semiconductor substrate 110 in a honeycomb structure and a support 130 having a plurality of open areas OP is illustrated ) to fit between each of the plurality of first capacitors ( Fig. 1A #120 ); and a high-k material surrounding each of the pluralities of first capacitors and second capacitors ( [0058] The lower support 132 may include an insulating layer, for example, silicon oxide, silicon nitride, or silicon oxynitride. For example, the lower support 132 may include the same material as that of the support 130; silicon oxynitride has a higher k value than silicon nitride so qualifies for this feature ).
Regarding claim 3, Kim teaches the DRAM device of claim 2 ( as discussed above), wherein each of the pluralities of first capacitors ( Fig. 1A #120 ) and second capacitors ( [0035] Therefore, as illustrated in FIG. 1A, upper surfaces of the plurality of lower electrodes 120 may be exposed through the support 130) are separated from adjacent capacitors by a spacer material ( Fig. 1A #130 ).
Regarding claim 6, Kim teaches the DRAM device of claim 2 ( as discussed above), further comprising an access point ( Fig. 1A contact plugs #111 ) located between the plurality of first capacitors ( Fig. 1A #120 ) and between the plurality of second capacitors ( [0035] Therefore, as illustrated in FIG. 1A, upper surfaces of the plurality of lower electrodes 120 may be exposed through the support 130).
Regarding claim 7, Kim teaches the DRAM device of claim 2 ( as discussed above), wherein the plurality of first capacitors ( Fig. 1A #120 ) and the plurality of second capacitors ( [0035] Therefore, as illustrated in FIG. 1A, upper surfaces of the plurality of lower electrodes 120 may be exposed through the support 130 ) independently comprise a metal selected from one or more of tungsten (W) or titanium nitride (TiN) ( [0110] A conductive material of which the plurality of lower electrodes 120 are formed may include any one or any combination of metal nitride and metal. The conductive material may include any one or any combination of, for example, TiN, Ru, TaN, WN, Pt, and Ir ).
Regarding claim 9, Kim teaches a method of forming a DRAM device, the method comprising: forming a stack on an etch stop layer ( Fig. 6B #115L ) on a substrate ( Fig. 6B #110 ), the stack comprising a core layer ( Fig. 6B interlayer insulating layer #113 ) on an etch stop layer ( Fig. 6B #115L ) on a substrate ( Fig. 6B #110 ), a support layer ( Fig. 6B support #130L ) on a top surface of the core layer ( Fig. 6B #113 ), a hardmask layer ( Fig. 6B #142; [0106] Referring to FIGS. 7A and 7B, the first photoresist pattern PR1 may be removed. After removing the first photoresist pattern PR1 (refer to Fig. 6B ), the first sacrificial layer 141L (refer to Fig. 6B ), the support forming layer 130L (refer to Fig. 6B ), the mold layer 125L (refer to Fig. 6B ), and the etch stop layer 115L (refer to Fig. 6B ) are sequentially etched by using the second sacrificial pattern 142 as an etching mask ) on the support layer ( Fig. 6B #125L ), a hardmask opening layer on the hardmask layer ( as shown in Fig. 6B ), a second support layer ( Fig. 6B #132 ) on the hardmask opening layer ( as shown in Fig. 2 ), a DARC layer ( [0103] In addition, an antireflective coating ( ARC ) may be formed on the second sacrificial layer ) on the second support layer ( Fig. 6B #132 ), and a photoresist layer ( Fig. 6B PR1 ) on the DARC layer ( as described above ); etching a first set of hexagonal holes in the stack ( as shown in Fig. 7A ), the first set of hexagonal holes extending from a top surface of the photoresist layer to a top surface of the substrate ( as shown in Fig. 7A ); conformally depositing spacer layer in the first set of hexagonal holes ( Fig. 10B third sacrificial layer #143 ); etching the stack and spacer layer to remove the spacer layer from a bottom surface of the first set of hexagonal holes ( [0125] Referring to FIGS. 12A and 12B, the third sacrificial pattern 143M (refer to FIG. 11B) and the mold pattern 125 (refer to FIG. 11B) are removed through the wet etching process ); patterning and etching a second set of hexagonal holes adjacent to the first set of hexagonal holes ( [0127] The wet etching solution permeates into the plurality of second open holes G2 (refer to FIG. 12B) formed in the third sacrificial pattern 143M (refer to FIG. 11B) and the plurality of open areas OP formed in the support 130 and wet etches the third sacrificial pattern 143M (refer to FIG. 11B) and the mold pattern 125 (refer to FIG. 11B) ); depositing a high-k material between the second set of hexagonal holes and the first set of hexagonal holes ( Fig. 12B #150; [0132] The dielectric layer 150 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a high-k material ); and forming a top electrode ( Fig. 13B upper electrode #160 ) on the second set of hexagonal holes and the first set of hexagonal holes ( as shown in Fig. 13B ) to form a first set of capacitors and a second set of capacitors ( [0132] The dielectric layer 150 may electrically isolate the plurality of lower electrodes 120 from the upper electrode 160 formed in the subsequent process so that the plurality of lower electrodes 120 and the upper electrode 160 may function as a capacitor ).
Regarding claim 11, Kim teaches the method of claim 9 ( as discussed above), wherein the support layer ( Fig. 6B support #130L ) and second support layer ( Fig. 6B #132 ) independently comprise one or more of silicon carbonitride (SiCN), silicon nitride (SiN), and silicon oxide (SiO2) ( [0058] The lower support 132 may include an insulating layer, for example, silicon oxide, silicon nitride, or silicon oxynitride; [0101] Then, a support forming layer 130L is formed on the mold layer 125L. The support forming layer 130L may include, for example, silicon nitride or polysilicon ).
Regarding claim 12, Kim teaches the method of claim 9 ( as discussed above), wherein the hardmask layer ( Fig. 6B #142 ) comprises one or more of silicon oxide (SiOx), silicon carbide (SiC), carbon doped hydrogenated silicon oxide (SiOCH), boron (B), and boron nitride (BN) ( [0103] The second sacrificial layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or polysilicon. In addition, an antireflective coating (ARC) may be formed on the second sacrificial layer ).
Regarding claim 14, Kim teaches the method of claim 9 ( as discussed above), wherein the top electrode comprises one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) ( [0133] A conductive material that becomes the upper electrode 160 may include any one or any combination of metal nitride and metal. For example, the upper electrode 160 may include any one or any combination of TiN, Ru, TaN, WN, Pt, and Ir ).
Regarding claim 15, Kim teaches the method of claim 9 ( as discussed above), wherein the first set of capacitors and the second set of capacitors are separated from adjacent capacitors by the high-k material ( Fig. 1A: #130 ; [0129] As described above, each of the plurality of lower electrodes 120, the plurality of open areas OP, and the plurality of support patterns SP may be arranged in a honeycomb structure ).
Regarding claim 19, Kim teaches the method of claim 9 ( as discussed above), wherein the first set of capacitors ( Fig. 1A #120 ) and the second set of capacitors ( [0035] Therefore, as illustrated in FIG. 1A, upper surfaces of the plurality of lower electrodes 120 may be exposed through the support 130 ) independently comprise a metal selected from one or more of tungsten (W) or titanium nitride (TiN) ( [0110] A conductive material of which the plurality of lower electrodes 120 are formed may include any one or any combination of metal nitride and metal. The conductive material may include any one or any combination of, for example, TiN, Ru, TaN, WN, Pt, and Ir ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 16 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0115376 A1; 05/2021 in view of Dai; US 2021/0074706 A1; 11/2020
Claim 4: Kim discloses the DRAM device of claim 2 ( as discussed above).
Kim does not appear to disclose an average gap between adjacent capacitors is in a range of 12 nm to 20 nm.
However, Dai teaches an average gap between adjacent capacitors is in a range of 12 nm to 20 nm ( [0056] A maximum width of the capacitor holes 601 may range from 16 nm to 21 nm; the height of the capacitor holes 601 may range from 800 nm to 1,600 nm; and the distance between adjacent capacitor holes 601 ranges from 30 nm to 50 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Dai with Kim to implement an average gap between adjacent capacitors is in a range of 12 nm to 20 nm because MPEP 2144.05 (I) Similarly, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985) (Court held as proper a rejection of a claim directed to an alloy of "having 0.8% nickel, 0.3% molybdenum, up to 0.1% iron, balance titanium" as obvious over a reference disclosing alloys of 0.75% nickel, 0.25% molybdenum, balance titanium and 0.94% nickel, 0.31% molybdenum, balance titanium. "The proportions are so close that prima facie one skilled in the art would have expected them to have the same properties."). See also Warner-Jenkinson Co., Inc. v. Hilton Davis Chemical Co., 520 U.S. 17, 41 USPQ2d 1865 (1997) (under the doctrine of equivalents, a purification process using a pH of 5.0 could infringe a patented purification process requiring a pH of 6.0-9.0); In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%); In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205-206 (CCPA 1946) (prior art showed an angle in a groove of up to 90° and an applicant claimed an angle of no less than 120°); In re Becket, 88 F.2d 684 (CCPA 1937) ("Where the component elements of alloys are the same, and where they approach so closely the same range of quantities as is here the case, it seems that there ought to be some noticeable difference in the qualities of the respective alloys."); In re Dreyfus, 73 F.2d 931, 934, 24 USPQ 52, 55 (CCPA 1934)(the prior art, which taught about 0.7:1 of alkali to water, renders unpatentable a claim that increased the proportion to at least 1:1 because there was no showing that the claimed proportions were critical); In re Lilienfeld, 67 F.2d 920, 924, 20 USPQ 53, 57 (CCPA 1933)(the prior art teaching an alkali cellulose containing minimal amounts of water, found by the Examiner to be in the 5-8% range, the claims sought to be patented were to an alkali cellulose with varying higher ranges of water (e.g., "not substantially less than 13%," "not substantially below 17%," and "between about 13[%] and 20%"); K-Swiss Inc. v. Glide N Lock GmbH, 567 Fed. App'x 906 (Fed. Cir. 2014)(reversing the Board's decision, in an appeal of an inter partes reexamination proceeding, that certain claims were not prima facie obvious due to non-overlapping ranges); In re Brandt, 886 F.3d 1171, 1177, 126 USPQ2d 1079, 1082 (Fed. Cir. 2018)(the court found a prima facie case of obviousness had been made in a predictable art wherein the claimed range of "less than 6 pounds per cubic feet" and the prior art range of "between 6 lbs./ft3 and 25 lbs./ft3" were so mathematically close that the difference between the claimed ranges was virtually negligible absent any showing of unexpected results or criticality ).
Claim 16: Kim discloses the method of claim 9 ( as discussed above).
Kim does not appear to disclose an average gap between adjacent capacitors is in a range of 12 nm to 20 nm.
However, Dai teaches an average gap between adjacent capacitors is in a range of 12 nm to 20 nm ( [0056] A maximum width of the capacitor holes 601 may range from 16 nm to 21 nm; the height of the capacitor holes 601 may range from 800 nm to 1,600 nm; and the distance between adjacent capacitor holes 601 ranges from 30 nm to 50 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Dai with Kim to implement an average gap between adjacent capacitors is in a range of 12 nm to 20 nm because MPEP 2144.05 (I) Similarly, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985) (Court held as proper a rejection of a claim directed to an alloy of "having 0.8% nickel, 0.3% molybdenum, up to 0.1% iron, balance titanium" as obvious over a reference disclosing alloys of 0.75% nickel, 0.25% molybdenum, balance titanium and 0.94% nickel, 0.31% molybdenum, balance titanium. "The proportions are so close that prima facie one skilled in the art would have expected them to have the same properties."). See also Warner-Jenkinson Co., Inc. v. Hilton Davis Chemical Co., 520 U.S. 17, 41 USPQ2d 1865 (1997) (under the doctrine of equivalents, a purification process using a pH of 5.0 could infringe a patented purification process requiring a pH of 6.0-9.0); In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%); In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205-206 (CCPA 1946) (prior art showed an angle in a groove of up to 90° and an applicant claimed an angle of no less than 120°); In re Becket, 88 F.2d 684 (CCPA 1937) ("Where the component elements of alloys are the same, and where they approach so closely the same range of quantities as is here the case, it seems that there ought to be some noticeable difference in the qualities of the respective alloys."); In re Dreyfus, 73 F.2d 931, 934, 24 USPQ 52, 55 (CCPA 1934)(the prior art, which taught about 0.7:1 of alkali to water, renders unpatentable a claim that increased the proportion to at least 1:1 because there was no showing that the claimed proportions were critical); In re Lilienfeld, 67 F.2d 920, 924, 20 USPQ 53, 57 (CCPA 1933)(the prior art teaching an alkali cellulose containing minimal amounts of water, found by the Examiner to be in the 5-8% range, the claims sought to be patented were to an alkali cellulose with varying higher ranges of water (e.g., "not substantially less than 13%," "not substantially below 17%," and "between about 13[%] and 20%"); K-Swiss Inc. v. Glide N Lock GmbH, 567 Fed. App'x 906 (Fed. Cir. 2014)(reversing the Board's decision, in an appeal of an inter partes reexamination proceeding, that certain claims were not prima facie obvious due to non-overlapping ranges); In re Brandt, 886 F.3d 1171, 1177, 126 USPQ2d 1079, 1082 (Fed. Cir. 2018)(the court found a prima facie case of obviousness had been made in a predictable art wherein the claimed range of "less than 6 pounds per cubic feet" and the prior art range of "between 6 lbs./ft3 and 25 lbs./ft3" were so mathematically close that the difference between the claimed ranges was virtually negligible absent any showing of unexpected results or criticality ).
Claims 5, 17, and 18 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0115376 A1; 05/2021 in view of Yang; US 2016/0284725 A1; 03/2015
Claim 5: Kim discloses the DRAM device of claim 2 ( as discussed above).
Kim does not appear to disclose further comprising wordlines and bitlines connected to each of the capacitors, the wordlines having a pitch equal to less than 0.6 x a bitline pitch.
However, Yang teaches further comprising wordlines ( Fig. 6B word lines #610 ) and bitlines ( Fig. 6B bit lines #608 ) connected to each of the capacitors ( [0080] It is to be understood in the present disclosure that the principles described can be applied outside the context of NAND-type devices described in exemplary embodiments, including NOR-type devices, other memory storage devices, floating gate memory devices, charge trapping memory devices, non-volatile memory devices, and/or embedded memory devices ), the wordlines having a pitch equal to less than 0.6 x a bitline pitch ( [0048] The bit line pitch may be about 80-160 nm and the word line pitch may be about 80-160 nm in example embodiments ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yang with Kim to implement further comprising wordlines and bitlines connected to each of the capacitors, the wordlines having a pitch equal to less than 0.6 x a bitline pitch because this maximizes storage capacity and enhances density.
Claim 17: Kim discloses the method of claim 9 ( as discussed above).
Kim does not appear to disclose further comprising forming wordlines and bitlines connected to each of the capacitors.
However, Yang teaches further comprising forming wordlines ( Fig. 6B word lines #610 ) and bitlines ( Fig. 6B bit lines #608 ) connected to each of the capacitors ( [0080] It is to be understood in the present disclosure that the principles described can be applied outside the context of NAND-type devices described in exemplary embodiments, including NOR-type devices, other memory storage devices, floating gate memory devices, charge trapping memory devices, non-volatile memory devices, and/or embedded memory devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yang with Kim to implement further comprising forming wordlines and bitlines connected to each of the capacitors because this enables individual addressing, reading, and writing of data.
Claim 18: Kim and Yang disclose the method of claim 17 ( as discussed above).
Kim does not appear to disclose the wordlines have a pitch equal to less than 0.6 x a bitline pitch.
However, Yang teaches the wordlines having a pitch equal to less than 0.6 x a bitline pitch ( [0048] The bit line pitch may be about 80-160 nm and the word line pitch may be about 80-160 nm in example embodiments ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yang with Kim to implement the wordlines have a pitch equal to less than 0.6 x a bitline pitch because this maximizes storage capacity and enhances density.
Claims 8 and 20 are rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0115376 A1; 05/2021 in view of Kang et al.; US 12,532,453 B2; 09/2022
Claim 8: Kim discloses the DRAM device of claim 2 ( as discussed above).
Kim does not appear to disclose the high-k material comprises zirconium oxide (ZrOx).
However, Kang teaches the high-k material comprises zirconium oxide (ZrOx) ( Col. 6 lines 30-43The dielectric layer DE may be referred to as a capacitor dielectric layer. High dielectric constant materials may include hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), titanium oxide (TiO.sub.2), tantalum oxide (Ta.sub.2O.sub.5), niobium oxide (Nb.sub.2O.sub.5) or strontium titanium oxide (SrTiO.sub.3))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kang with Kim to implement the high-k material comprises zirconium oxide (ZrOx) because the high dielectric constant of this material offers superior thermal stability, high radiation tolerance, and compatibility with atomic layer deposition.
Claim 20: Kim discloses the method of claim 9 ( as discussed above).
Kim does not appear to disclose the high-k material comprises zirconium oxide (ZrOx).
However, Kang teaches the high-k material comprises zirconium oxide (ZrOx) ( Col. 6 lines 30-43The dielectric layer DE may be referred to as a capacitor dielectric layer. High dielectric constant materials may include hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), aluminum oxide (Al.sub.2O.sub.3), lanthanum oxide (La.sub.2O.sub.3), titanium oxide (TiO.sub.2), tantalum oxide (Ta.sub.2O.sub.5), niobium oxide (Nb.sub.2O.sub.5) or strontium titanium oxide (SrTiO.sub.3))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kang with Kim to implement the high-k material comprises zirconium oxide (ZrOx) because the high dielectric constant of this material offers superior thermal stability, high radiation tolerance, and compatibility with atomic layer deposition.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0115376 A1; 05/2021 in view of Chou et al.; US 2022/0108894 A1
Claim 10: Kim discloses the method of claim 9 ( as discussed above).
Kim does not appear to disclose the core layer comprises a carbon material.
However, Chou teaches the core layer comprises a carbon material ( Fig. 1A #140; [0019] A core layer 140 is formed over the semiconductor hard mask layer 130. In some embodiments, the core layer 140 is made of a carbon -rich material such as carbon or spin-on coating (SOC) carbon )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chou with Kim to implement the core layer comprises a carbon material because of the superior electrical conductivity, high thermal stability, and ability to form stable conductive filaments.
Claim 13 is rejected under U.S.C. 103 as being unpatentable over Kim et al.; US 2022/0115376 A1; 05/2021 in view of Miyahara et al.; US 2018/0090319 A1; 09/2017
Claim 13: Kim discloses the method of claim 9 ( as discussed above).
Kim does not appear to disclose the hardmask layer comprises boron (B) or boron nitride (BN).
However, Miyahara teaches the hardmask layer comprises boron (B) or boron nitride (BN) ( [0021] The hard mask according to the present embodiment is made of a boron-based film and is typically a CVD film ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Miyahara with Kim to implement the hardmask layer comprises boron (B) or boron nitride (BN) because extreme etching resistance, high-aspect-ratio patterning and superior mechanical stability are possible with these materials.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817