DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/01/2023 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-11 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Asenov (2014/0027854). Re claim 1, Asenov teaches a transistor (Fig. 2), comprising: a semiconductor layer (221); a source region ([19], 29), a drain region ([19], 29), and a body region (22, 23) arranged in the semiconductor layer (221); and a gate region (25, 26) topping the body region (22, 23); wherein the body region (22, 23) comprises a first doped layer (22) and a second layer (23) between the first doped layer (22) and the gate region (25, 26), the second layer (23) being an epitaxial layer [19], and the second layer (23) being less heavily doped [19-20] than the first doped layer (22).
Re claim 2, Asenov teaches the transistor according to claim 1, wherein a doping of the first doped layer (22) is from 2 to 10 times heavier than a doping of the second layer ([20], 23).
Re claim 3, Asenov teaches the transistor according to claim 1, wherein a doping of the first doped layer (22) is from 5 to 10 times heavier than a doping of the second layer ([20], 23).
Re claim 5, Asenov teaches the transistor according to claim 1, wherein the second layer (23) is non-intentionally doped [19].
Re claim 6, Asenov teaches the transistor according to claim 1, wherein the first doped layer (22) is a layer doped by ion implantation [19].
Re claim 7, Asenov teaches the transistor according to claim 1, wherein the first doped layer is a doped epitaxial layer [19-20].
Re claim 8, Asenov teaches the transistor according to claim 1, wherein the source region, the drain region, and the second layer are flush with a first surface of the semiconductor layer (Fig. 2). Re claim 9, Asenov teaches the transistor according to claim 1, further comprising an insulating layer (21) in contact with a second surface of the semiconductor layer (221), the first doped layer (22) being in contact with said insulating layer (21).
Re claim 10, Asenov teaches the transistor according to claim 1, further comprising a gate insulator layer (24) between the gate region (25, 26) and the second layer (23).
Re claim 11, Asenov teaches the transistor according to claim 1, wherein the second layer (23) comprises a channel-forming region of the transistor [17-19].
Re claim 14, Asenov teaches an electronic device comprising at least one transistor according to claim 1 ([17], Fig. 2).
Claim(s) 16-20 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Asenov (2014/0027854).
Re claim 16, Asenov teaches a method of manufacturing a transistor (Figs. 4A-D) which comprises a source region [44], a drain region [44] and a body region (42, 43) arranged in a semiconductor layer (421), and a gate region ([49], 453) topping the body region (42, 43), the method comprising: forming the body region (42, 43) by: forming a first doped layer (42); and forming by epitaxial growth a second layer ([47], 43) above the first doped layer (42), the epitaxial growth being configured so that the second layer (43) is less heavily doped than the first doped layer [47].
Re claim 17, Asenov teaches the method according to claim 16, wherein the epitaxial growth is configured so that the second layer (43) is non-intentionally doped [47]. Re claim 18, Asenov teaches the method according to claim 16, wherein forming the body region (42, 43) comprises: etching an initial semiconductor layer (421) down to a depth smaller than a thickness of said initial semiconductor layer (Fig. 4B); forming the first doped layer (42) by doping through ion implantation the non-etched thickness of the initial semiconductor layer [46]; and forming by epitaxial growth [47] the second layer (43) after doping of the first doped layer (42); wherein a thickness of the second layer is substantially equal to or slightly greater than the depth of the etching (Figs. 4B-D).
Re claim 19, Asenov teaches the method according to claim 18, wherein forming the body region (42, 43) further comprises performing an anneal after the doping [32, 43].
Re claim 20, Asenov teaches the method according to claim 16, wherein forming the body region (42, 43) comprises: etching an initial semiconductor layer (421) across substantially an entire thickness of said initial semiconductor layer (Figs. 4B-C); forming the first doped layer (42) by epitaxial growth with a dopant on the etched initial semiconductor layer (Figs. 4B-C); and forming by epitaxial growth [47] the second layer (43) after the epitaxial growth with a dopant of the first doped layer (22); wherein a thickness of the first doped layer (22) is smaller than a thickness of the initial semiconductor layer (421), and wherein a thickness of the second layer (43) is substantially equal to or greater than a thickness of the initial semiconductor layer minus the thickness of the first doped layer [26-43].
Re claim 24, Asenov teaches the method according to claim 16, further comprising forming the gate region after forming the body region [48].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Asenov (2014/0027854) in view of the following reasons.
Re claim 4, Asenov teaches the transistor according to claim 1, wherein a thickness of the second layer (23) is between 10 nm and 20 nm [21].
Asenov does not explicitly teach wherein a thickness of the first doped layer is between 40 nm and 50 nm. However, Applicant has not shown wherein a thickness of the first doped layer between 40 nm and 50 nm has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to adjust the thickness of the first doped layer so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Re claim 15, Asenov does not explicitly teach a radio frequency switch comprising at least one transistor according to claim 1. However, it would have been obvious to one of ordinary skill in the art as of the effective filling date of the claimed invention to use the device of Asenov in a radio frequency switch since it has been held that a choosing from a finite number of known options is within the technical grasp of a person having ordinary skill in the art and is not patentable over the prior art. See MPEP 2143(E).
Allowable Subject Matter
Claims 12-13 and 21-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 12, Asenov teaches the transistor according to claim 1, yet remains explicitly silent to further comprising a diffusion stop layer between the first doped layer and the second layer.
Claim 13 is objected to for at least depending from objected claim 12.
Re claim 21, Asenov teaches the method according to claim 16, yet remains explicitly silent to further comprising depositing a diffusion stop layer between the first doped layer and the second layer.
Claims 22-23 are objected to for at least depending from objected claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897