DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, claims 1-4, 9-14, and 18-20 in the reply filed on 02/11/2026 is acknowledged.
Claims 5-8 and 15-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/11/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-14, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwak et. al., U.S. Pat. Pub. 2021/0036087, hereafter Kwak.
Regarding claim 1, Kwak discloses (Figs 4, 5A, 5B, 6, 8, 10-11) a display device (title) comprising:
a substrate [100] having a non-rectangular display area [DA] (see Fig. 5A);
a plurality of pixels [PC-U] disposed in the display area [DA] and disposed in a plurality of pixel columns (vertical columns of pixels shown in Fig. 5A) extending along a first direction (vertically) and a plurality of pixel rows (horizontal rows of pixels [PC-U]) extending along a second direction (horizontally) crossing the first direction; and
a compensation pattern [CLM] disposed adjacent to a pixel disposed in an uppermost pixel row among the plurality of pixels extending in the first direction (along virtual line [VL1]).
Regarding claim 2, Kwak further discloses (Fig. 10) wherein the compensation pattern [CLM] includes: a first metal pattern [510] disposed on the substrate [100]; and a second metal pattern [520] disposed on the first metal pattern [510], wherein a first compensation capacitor is formed in an area where the first metal pattern [510] and the second metal pattern [520] overlap each other.
Regarding claim 3, Kwak further discloses (Fig. 4) wherein, the plurality of pixels [PC-U] includes a first transistor [TFT1] and a second transistor [TFT2], wherein the first transistor [TFT1] includes a first active pattern [AS], a first gate pattern [GE1], a first source electrode [S1], and a first drain electrode [D1] (par. [0103]), and wherein
the first metal pattern [510] includes a same material as the first gate pattern (par. [0163]-[0165]).
Regarding claim 4, Kwak further discloses (Fig. 4) further comprising: a capacitor electrode pattern [CE1], [CE2] overlapping the first gate pattern [GE1], wherein,
a storage capacitor [Cst] is formed in an area where the capacitor electrode pattern [CE2] and the first gate pattern [GE1] overlap each other, and wherein
the second metal pattern [520] includes a same material as the capacitor electrode pattern. (par. [0164]).
Regarding claim 9, Kwak further discloses (Fig. 6) wherein the compensation pattern [CLM1], [CLM2], [CLM3] is disposed to correspond to each of the plurality of pixel columns [PC1]-[PC3].
Regarding claim 10, Kwak further discloses (Figs 7A, B, 8) further comprising:
a plurality of data lines [DL] connected to the plurality of pixels located in a corresponding pixel column [PC1], [PC2], [PC3], extending in the first direction (vertically), and spaced apart from each other in the second direction (horizontal, see Fig. 8, which is a layout),
wherein each of the plurality of data lines [DL] has a different internal capacitance, and wherein the compensation pattern [CLM1-3] provides a compensation capacitance for compensating for a deviation in an internal capacitance between the plurality of data lines [DL] (par. [0139]).
Regarding claim 11, Kwak further discloses (Fig. 15, par. [0183]) wherein the compensation capacitance increases as a distance of a corresponding pixel column from a virtual line passing through a center of the display area and extending in the first direction increases.
Regarding claim 12, Kwak discloses (Figs 4, 5A, 5B, 6, 8, 10-11) a display device (title) comprising:
a substrate [100] having a non-rectangular display area [DA] (Fig. 5A);
a plurality of pixels [PC-U] disposed in the display area [DA] and disposed in a plurality of pixel columns (vertical columns of pixels shown in Fig. 5A) extending along a first direction (vertically) and a plurality of pixel rows (horizontal rows of pixels [PC-U]) extending along a second direction (horizontally) crossing the first direction; and
a compensation pattern [CLM] disposed adjacent to a pixel disposed in an uppermost pixel row among the plurality of pixels extending in the first direction (along virtual line [VL1]).
a compensation pattern [CLM] including a first sub compensation pattern [CLM1] disposed adjacent to a first sub pixel [PC1] included in a pixel disposed in an uppermost pixel row among the plurality of pixels in the first direction (along virtual line [VL1]) and a second sub compensation pattern [CLM2] disposed adjacent to a second sub pixel [PC2] included in the pixel and having an internal capacitance different from an internal capacitance of the first sub pixel (par. [0183]).
Regarding claim 13, Kwak further discloses (Fig. 15, par. [0183]) wherein each of the first sub compensation pattern and the second sub compensation pattern provides a different compensation capacitance.
Regarding claim 14, Kwak further discloses (Fig. 4) wherein, the plurality of pixels [PC-U] includes a first transistor [TFT1] and a second transistor [TFT2], wherein the first transistor [TFT1] includes a first active pattern [AS], a first gate pattern [GE1], a first source electrode [S1], and a first drain electrode [D1] (par. [0103]), and wherein
the compensation pattern includes:
a first metal pattern [510] disposed on the substrate [100]; and
a second metal pattern [520] disposed on the first metal pattern [510],
wherein a first compensation capacitor [CLM] is formed in an area where the first metal pattern [510] and the second metal pattern [520] overlap each other, and
wherein the first metal pattern [510] includes a same material as the first gate pattern (par. [0163]-[0165]).
Regarding claim 18, Kwak further discloses (Fig. 4) wherein the compensation pattern [CLM1]-[CLM2] is disposed to correspond to each pixel column [PC1]-[PC3].
Regarding claim 19, Kwak further discloses (Figs 7,8)
19. The display device of claim 18, further comprising:
a plurality of data lines [DL] connected the plurality of pixels [PCn] located in a corresponding pixel column, extending in the first direction(vertically) , and spaced apart from each other in the second
direction (horizontally),
wherein each of the plurality of data lines has a different internal capacitance (due to different size), and wherein the compensation pattern provides a compensation capacitance for compensating for a deviation of the internal capacitance between the plurality of data lines [DL] (see Figs 7A, 7B, par. [0139].
Regarding claim 20, Kwak further discloses (Fig. 15, par. [0183]) wherein the compensation capacitance increases as a distance of a corresponding pixel column from a virtual line passing through a center of the display area and extending in the first direction increases (the area of capacitor electrodes increases, so the capacitance increases, all other things being equal).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VICTOR V BARZYKIN/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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