DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Rejections - 35 USC § 112 3
A. Claim 1-11 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. 3
IV. Claim Rejections - 35 USC § 102 5
A. Claims 1-3 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2006/0079033 (“Machida”). 5
V. Claim Rejections - 35 USC § 103 6
A. Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Machida, as evidenced by US 2003/0155629 (“Giust”) for only claim 8. 7
B. Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Machina in view of US 2021/0272986 (“Do”). 11
C. Claims 1-3, 5-7, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2021-136299 A (“Noguchi”) in view of Machida. 13
VI. Pertinent Prior Art 15
Conclusion 16
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of invention group I, claims 1-11, in the reply filed on 04/28/2026 is acknowledged.
Claims 12-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
III. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claim 1-11 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 1 reads,
1. A manufacturing method for a thin film transistor, the method comprising:
[1] a step of forming a buffer layer on a substrate;
[2] a step of forming a hydrogenated amorphous silicon layer on the buffer layer;
[3] a step of performing blue laser annealing on the hydrogenated amorphous silicon layer; and
[4] a step of forming a semiconductor layer by doping parts of the hydrogenated amorphous silicon layer with impurities,
[5] wherein in the step of performing blue laser annealing, dehydrogenation and crystallization are performed in the hydrogenated amorphous silicon layer.
There is not written descriptive support for step [4], i.e. “forming a semiconductor layer by doping parts of the hydrogenated amorphous silicon layer with impurities”, sufficient to show that Applicant was in possession of this invention. The Instant Specification only discloses doping the already dehydrogenated, crystallized silicon layer to form the source and drain regions of the TFT, as shown in Figs. 3-6 (p. 15, line 19 to p. 19, line 9 or equally ¶¶ 74-84 of US 2024/0274678, which is the pre-grant publication of the Instant Application). Once the hydrogenated amorphous silicon layer 130a has been dehydrogenated and crystallized by the BLA to form the silicon layer 130, it no longer hydrogenated amorphous silicon. As such, there is not support in the Instant Application sufficient to show that the Instant Inventors were in possession of “doping parts of the hydrogenated amorphous silicon layer with impurities” because it is already polycrystalline silicon.
The invention is, for purposes of the “written description” inquiry, whatever is now claimed. Vas-Cath, Inc. v. Mahurkar, 935 F.2d 1555, 1563-64 (Fed. Cir. 1991). One shows “possession” by descriptive means such as words, structures, figures, diagrams, and formulas that fully set forth the claimed invention. Lockwood v. American Airlines, Inc., 107 F.3d 1565, 1572 (Fed. Cir. 1997). It is not sufficient for purposes of the written description requirement that the disclosure, when combined with the knowledge in the art, would lead one to speculate as to modifications that the inventor might have envisioned, but failed to disclose. Id. But, a description that merely renders an invention obvious does not satisfy the written description requirement under Section 112. Ariad Pharms., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1352 (Fed. Cir. 2010) (en banc). Here, doping the hydrogenated amorphous silicon layer with impurities to form a semiconductor layer is, at best, obvious.
Claims 2-11 are rejected for including the same unsupported limitation by depending from claim 1 either directly or indirectly.
IV. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1-3 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2006/0079033 (“Machida”).
With regard to claims 1-3 and 11, Machida discloses,
1. A manufacturing method for a thin film transistor [title; ¶ 5, 25; e.g. Fig. 4B], the method comprising:
[1] a step of forming a buffer layer 3 on a substrate 1 [¶ 27; Fig. 1A];
[2] a step of forming a hydrogenated amorphous silicon layer 5 on the buffer layer [¶¶ 28-35; Fig. 1A];
[3] a step of performing blue laser [i.e. 350 nm to 470 nm (¶ 39)] annealing on the hydrogenated amorphous silicon layer 5 [¶¶ 36-53, 77; Figs. 1B-1C, 6B]; and
[4] a step of forming a semiconductor layer 11 by doping parts of the hydrogenated amorphous silicon layer 5 with impurities [¶¶ 58-59],
[5] wherein in the step of performing blue laser annealing, dehydrogenation and crystallization are performed in the hydrogenated amorphous silicon layer [abstract; ¶¶ 15, 17, 46, 51, 73, 77-78].
2. The manufacturing method for the thin film transistor according to claim 1, wherein the dehydrogenation and the crystallization are performed at the same time [abstract; ¶¶ 15, 17, 46, 51, 73, 77-78].
3. The manufacturing method for the thin film transistor according to claim 1, wherein in the step of performing blue laser annealing, a blue laser scans the semiconductor layer one time to three times [¶¶ 52-53; Figs. 2, 3].
11. The manufacturing method for the thin film transistor according to claim 1, further comprising: a step of forming a gate electrode 7/9 so as to overlap the semiconductor layer 5 [¶¶ 54-55; Fig. 1D].
V. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Machida, as evidenced by US 2003/0155629 (“Giust”) for only claim 8.
Claims 5-6 reads,
5. The manufacturing method for the thin film transistor according to claim 1, wherein a blue laser which is used in the step of performing blue laser annealing has a wavelength range from 400 nm to 500 nm.
6. The manufacturing method for the thin film transistor according to claim 5, wherein the blue laser which is used in the step of performing blue laser annealing has a wavelength range from 440 nm to 450 nm.
The prior art of Machida, as explained above, discloses each of the features of claims 1 as well as a wavelength range of 350 nm to 470 nm for the laser (¶ 39), which overlaps the claimed range in claim 5. In addition, the range claimed in claim 6 falls within the range disclosed in Machida.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
“[U]nexpected results [relied upon to rebut a prima facie case of obviousness].., must be shown to be unexpected compared with the closest prior art.” In re Baxter Travenol Labs, 952 F.2d 388, 392 (Fed. Cir. 1991)(citation omitted). Such evidence must be commensurate in scope with the degree of patent protection desired. In re Grasselli, 713 F.2d 731,743 (Fed. Cir. 1983). In addition, the difference in results relied upon to establish nonobviousness must be shown to be truly unexpected by one of ordinary skill in the art. Pfizer Inc. v. Apotex Inc., 480 F.3d 1348, 1371 (Fed. Cir. 2007). Thus, it is not enough to merely show that there is a difference-- even a significant difference. Rather, the difference in results must be shown to be unexpected by one of ordinary skill in the art. In re Harris, 409 F.3d 1339, 1344 (Fed. Cir. 2005).
Here, there is no evidence of record to show that the wavelength ranges of either of 400 nm to 500 nm or of 440 nm to 450 nm—alone, in isolation from the collection of “SPD” laser annealing conditions asserted in the Instant Application as providing unexpected results—would provide unexpected results relative to the closest prior art range.
Further with regard to claim 6, the selection of the range of 440 nm to 450 nm is obvious because it is a matter of determining optimum process condition by routine experimentation with a limited number of species. See In re Jones, 162 USPQ 224 (CCPA 1955)(the selection of optimum ranges within prior art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980)(discovery of optimum value of result effective variable in a known process is obvious).
This is all of the limitations of claims 5 and 6.
Claim 7 reads,
7. The manufacturing method for the thin film transistor according to claim 3, wherein the scan speed of the blue laser is 200 mm/s to 500 mm/s.
The prior art of Machida, as explained above, teaches each of the features of claim 3.
Machida discloses a scan speed range of 0.1 m/s to 10 m/s, i.e. 100 mm/s to 10,000 mm/s (¶ 41) specific example of 8.2 m/sec, i.e. 8200 mm/s (¶ 53). As such, the claimed range of 200 mm/s to 500 mm/s falls within the range disclosed in Machida.
As above, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
As to unexpected results, again, there is no evidence of record to show that the scan speed —alone, in isolation from the collection of “SPD” laser annealing conditions asserted in the Instant Application as providing unexpected results—would provide unexpected results relative to the closest prior art range.
With regard to claim 8, Machida further discloses,
8. The manufacturing method for the thin film transistor according to claim 7, wherein the step of performing blue laser annealing is performed at 950° C or higher.
Machida teaches that the hydrogenated amorphous silicon (a-Si:H) is melted by the laser annealing (Machida: ¶¶ 38, 43, 58). The melting point of a-Si:H is about 1100 ℃, as evidenced by Giust (¶ 61). As such, it is held, absent evidence to the contrary, that the laser annealing in Machida is necessarily, inherently performed at a temperature of 950 ℃ or higher, in order melt the a-Si:H. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
Claim 9 reads,
9. The manufacturing method for the thin film transistor according to claim 1, wherein the average grain size of the semiconductor layer formed through the blue laser annealing is 50 nm to 200 nm .
Machida states,
[0053] An experiment was conducted by irradiating a semiconductor thin film 5 (composed of a-Si:H), having a thickness of 50 nm and being formed by PE-CVD, with a laser beam traveling at a velocity vt of 8.2 m/sec and having an output equivalent to 1 J/cm2. The observation of the resulting film confirmed that the resulting film was a polycrystalline film containing aligned crescent-shaped crystal grains a having a width of 800 nm and a length of 100 nm in the laser beam traveling direction.
(Machida: ¶ 53; emphasis added)
As such, the claimed grain size range overlaps the prior art grain size range. As above, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP 2144.05(I)). In such a situation, Applicant must show that the particular ranges are critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. See In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). (See MPEP 2144.05(III)(A); emphasis added.)
With regard to claim 10, Machida further discloses,
10. The manufacturing method for the thin film transistor according to claim 9, wherein the thickness of the semiconductor layer is 50 nm to 800 nm [i.e. 50 nm (¶¶ 39, 53)].
B. Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Machina in view of US 2021/0272986 (“Do”).
Claims 5-6 reads,
5. The manufacturing method for the thin film transistor according to claim 1, wherein a blue laser which is used in the step of performing blue laser annealing has a wavelength range from 400 nm to 500 nm.
6. The manufacturing method for the thin film transistor according to claim 5, wherein the blue laser which is used in the step of performing blue laser annealing has a wavelength range from 440 nm to 450 nm.
The prior art of Machida, as explained above, discloses each of the features of claim 1, as well as a wavelength range of 350 nm to 470 nm for the laser (¶ 39), which overlaps the claimed range in claim 5. In addition, the range claimed in claim 6 falls within the range disclosed in Machida.
Do, like Machida, is directed to the same subject matter of blue laser annealing of an amorphous silicon layer 130 on a buffer layer 120 on a substrate 110 to form a polycrystalline silicon layer from which a TFT is formed (Do: Figs. 5A-5I). Do teaches that the wavelength range for the blue laser is from 440 nm to 460 nm (Do: ¶¶ 24, 33, 73, 90, 145, 154), e.g.
For example, the blue laser annealing may use a blue laser having a wavelength of about 360 nm to 480 nm. More specifically, the blue laser annealing may use a blue laser having a wavelength of about 440 nm to 460 nm.
(Do: ¶ 73: emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a wavelength range of 440 m to 460 nm in the process of Machida because (1) it falls within the range of 350 nm to 470 nm disclosed in Machida for the laser annealing and (2) Do teaches that 440 nm to 460 nm is suitable for the same purpose of crystallizing the amorphous silicon for subsequent use as a TFT.
This is all of the limitations of claims 5 and 6.
Claim 4 reads,
4. The manufacturing method for the thin film transistor according to claim 1, wherein the power of a blue laser which is used in the step of performing blue laser annealing is 7 W or higher.
Machida uses a 60 mW laser providing an average energy density of 17.7 mW/cm2 (Machida: ¶ 107) and does not consequently teach a laser having a power of 7 W or higher.
Do further teaches that the laser has a maximum output was 11.44 W, providing a power density of 110 kW/cm m2 (Do: ¶ 171).
Thus, in addition to using the wavelength range of 440 nm to 460 nm for the blue laser annealing in Machida, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a laser having a maximum output was 11.44 W, as taught by Do because it would be the substitution of one know blue laser for another known blue laser suitable for the same purpose of crystallizing amorphous silicon for producing TFTs. In addition, one having ordinary skill in the art would readily appreciate that a higher power laser would allow larger areas of amorphous silicon to be irradiated at one time, thereby reducing the time required to process a given semiconductor device. As such, Do may be seen as an improvement to Machida in this aspect. (See MPEP 2143.)
Claim 7 reads,
7. The manufacturing method for the thin film transistor according to claim 3, wherein the scan speed of the blue laser is 200 mm/s to 500 mm/s.
The prior art of Machida, as explained above, teaches each of the features of claim 3.
Machida discloses a scan speed range of 0.1 m/s to 10 m/s, i.e. 100 mm/s to 10,000 mm/s (¶ 41) specific example of 8.2 m/sec, i.e. 8200 mm/s (¶ 53).
Do further teaches that for an amorphous silicon layer of 50 nm to 300 nm thick, the scan speed can be “30 cm/s of more”, i.e. 300 mm/s or more (Do: ¶¶ 155-156) and an example at 400 mm/s (Do: ¶ 171).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a scan speed of, e.g. 400 mm/s, in the process of Machida because (1) it falls within the range of 100 mm/s to 10,000 mm/s disclosed in Machida (at ¶ 41) for the laser annealing and (2) Do teaches that 400 mm/s is suitable for the same purpose of crystallizing the amorphous silicon for subsequent use as a TFT.
C. Claims 1-3, 5-7, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2021-136299 A (“Noguchi”) in view of Machida.
With regard to claim 1, Noguchi discloses,
1. A manufacturing method for a thin film transistor [¶ 12; Fig. 2], the method comprising:
[1] a step of forming a buffer layer [SiN or SiO2 (¶ 32)] on a substrate [e.g. resin or glass (¶¶ 29-30)];
[2] a step of forming a hydrogenated amorphous silicon layer on the buffer layer [¶ 34];
[3] a step of performing blue laser annealing on the hydrogenated amorphous silicon layer [¶¶ 14-16, 18, 35-38, 41-43]; and
[4] a step of forming a semiconductor layer by doping parts of the hydrogenated amorphous silicon layer with impurities [¶¶ 32-33],
[5] wherein in the step of performing blue laser annealing, dehydrogenation and crystallization are performed in the hydrogenated amorphous silicon layer [¶¶ 9, 14, 18, 26, 36, 39, 41].
With regard to feature [3] of claim 1, Noguchi states that the source/drain regions are formed:
[0032] A film (underlayer) made of SiN (silicon nitride) and SiO2 (silicon oxide) is formed on the flexible substrate. Then, a channel portion and a source / drain portion made of a hydride amorphous silicon thin film are formed in the pixel portion 1 above the base layer, and the horizontal scanning portion 2 and the vertical scanning portion 3 are made of a polycrystalline silicon thin film. A channel part and a source / drain part are formed.
[0033] The channel portion and the source / drain portion are both hydrogenated amorphous silicon thin films formed by the same process. A gate insulating film is formed on the channel portion and the source / drain portion, and a gate electrode is formed on the portion of the gate insulating film that covers the channel portion. The TFT of the pixel unit 1, the horizontal scanning unit 2, and the vertical scanning unit 3 is configured by the channel unit, the source / drain unit, the gate insulating film, and the gate electrode.
(Noguchi: ¶¶ 32-33; emphasis added)
Noguchi does not state that the source/drain regions are formed by “doping” to hydrogenated amorphous silicon layer. However, it is exceedingly well known in the art that silicon source/drain regions must be doped in order to make then sufficiently conductive and in order to set the dimension of the channel formed between the source and drain regions.
Moreover, as explained above, Machida teaches doping the hydrogenated amorphous silicon layer with impurities to form the source/drain regions (Machida: ¶¶ 58-59).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to dope the source/drain regions of the hydrogenated amorphous silicon with impurities, in order to make functioning source/drain regions, as is exceedingly well known in the art as taught in Machida.
This is all of the limitations of claim 1.
With regard to claims 2, 3, 5-7, and 11, Noguchi further discloses,
2. The manufacturing method for the thin film transistor according to claim 1, wherein the dehydrogenation and the crystallization are performed at the same time [¶¶ 9, 14, 18, 26, 36, 39, 41].
3. The manufacturing method for the thin film transistor according to claim 1, wherein in the step of performing blue laser annealing, a blue laser scans the semiconductor layer one time to three times [two scans (¶¶ 18, 20, 43)].
5. The manufacturing method for the thin film transistor according to claim 1, wherein a blue laser which is used in the step of performing blue laser annealing has a wavelength range from 400 nm to 500 nm [¶ 15: “Preferably, the wavelength is 445 nm, the scanning speed is 300 mm/s …”].
6. The manufacturing method for the thin film transistor according to claim 5, wherein the blue laser which is used in the step of performing blue laser annealing has a wavelength range from 440 nm to 450 nm [¶ 15: “Preferably, the wavelength is 445 nm, the scanning speed is 300 mm/s …”; also ¶¶ 21, 41].
7. The manufacturing method for the thin film transistor according to claim 3, wherein the scan speed of the blue laser is 200 mm/s to 500 mm/s [¶ 15: “Preferably, the wavelength is 445 nm, the scanning speed is 300 mm/s …”; also, 500 mm/s ( ¶ 41)].
11. The manufacturing method for the thin film transistor according to claim 1, further comprising: a step of forming a gate electrode so as to overlap the semiconductor layer [¶ 33; Fig. 2].
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2024/0145243 (“Park”) is cited for teaching all of the process steps of claim 1 but does not teach what the wavelength of light emitted by the laser is. See Figs. 1-13 and at least ¶¶ 27, 43, 48, 51, 97, 99, 127.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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