DETAILED ACTION
Election/Restrictions
Applicant’s election of claims 1-10 and 12-20 in the reply filed on 3/9/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 9-11 and 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (Lee, US 2022/0352128 A1).
Regarding claim 1, Lee shows a method of fabricating an integrated circuit, the method comprising: forming a device layer (SBEOL as shown in FIG. 2M and [0027]) comprising a plurality of electronic devices ( chips 100 as shown in FIG. 2M); forming a metallization stack (wiring 158) on a front side of the device layer, the metallization stack including a plurality of patterned metal layers (wiring 158) spaced apart by intermetal dielectric material (insulation layer 158), the patterned metal layers electrically interconnecting the electronic devices (chip 100) of the device layer; forming a back side power distribution network ( wiring 182) on a back side of the device layer, the back side power distribution network including at least one back side patterned metal layer (metal 182) connected with power terminals of the plurality of semiconductor devices of the device layer; and forming copper vias ([0040]) passing through the device layer and contacting at least one patterned metal layer of the metallization stack (see FIG. 2M with respect to FGI. 4) , the copper vias being formed by a damascene process ( [0040] i.e. filling the 174 trench with metal).
Regarding claim 2, Lee shows a method of fabricating an integrated circuit, the method comprising, wherein the forming of the device layer includes forming the plurality of electronic devices ( chip 100) on and/or in a front side of a semiconductor substrate ( substrate 100), and the method further comprises: bonding the metallization stack ( wiring layer 152) to a carrier substrate ( element 30); and removing the semiconductor substate to expose the back side of the device layer (see FIG. 3C with respect to FIG. 2M).
Regarding claim 9, Lee shows a method of fabricating an integrated circuit, the method comprising: forming a device layer (SBEOL as shown in FIG. 2M and [0027]) comprising a plurality of electronic devices (chips 100); forming a metallization stack (wiring layer 152) disposed on a front side of the device layer and comprising a plurality of patterned metal layers spaced apart by intermetal dielectric material (dielectric layer 145), the metallization stack electrically interconnecting the electronic devices of the device layer; forming a back side power distribution network ( wiring 182) disposed on a back side of the device layer and connected to deliver electrical power to the plurality of semiconductor devices of the device layer; forming at least one signal transmission conductor ([0043]) disposed on the back side of the device layer; and forming copper vias passing through the device layer, the copper vias (via 174) electrically connecting the at least one signal transmission conductor with at least one patterned metal layer of the metallization stack (see FIG. 2M with respect to FIG. 3C).
Regarding claim 10, Lee shows a method of fabricating an integrated circuit, the method comprising, wherein the at least one signal transmission conductor comprises copper ([0040]).
Regarding claim 11, Lee shows a method of fabricating an integrated circuit, the method comprising, wherein the at least one patterned metal layer of the metallization stack comprises copper, and the metallization stack, the copper vias, and the at least one signal transmission conductor form at least one all-copper signal transmission path between devices of the device layer ( see FIG. 2M with respect to FIG. 3C and related text).
Regarding claim 15, Lee shows a method of fabricating an integrated circuit, the method comprising: forming a device layer (SBEOL as shown in FIG. 2M and [0027]) comprising a plurality of electronic devices (chips 100); disposing at least one dielectric layer ( insulation layer 145) on the device layer; etching via openings passing through the at least one dielectric layer ( see FIG. 2M) and through the device layer; electroplating copper on the at least one dielectric layer and filling the via openings, wherein the copper electroplated in the via openings form copper vias passing through the at least one dielectric layer and through the device layer and electrically connecting with devices of the device layer; and performing chemical mechanical polishing to remove the copper electroplated on the at least one dielectric layer ( see FIG. 2M and [0027-0045]).
Regarding claim 16, Lee shows a method of fabricating an integrated circuit, the method comprising: forming a metallization stack on the device layer wherein the device layer is interposed between the metallization stack and the at least one dielectric layer; wherein the via openings passing through the at least one dielectric layer and through the device layer land on at least one patterned metal layer of the metallization stack ( see FIG. 2M and [0027-0045]).
Regarding claim 17, Lee shows a method of fabricating an integrated circuit, the method further comprising: forming a power distribution network on the at least one dielectric layer (see FIG. 2M).
Regarding claim 18, Lee shows a method of fabricating an integrated circuit, the method further comprising: prior to the electroplating, etching trenches in the at least one dielectric layer, wherein the electroplating also fills the trenches to form a patterned metal layer of the power distribution network ( see FIG. 2M and [0027-0045]).
Regarding claim 19, Lee shows a method of fabricating an integrated circuit, the method further comprising forming at least one signal transmission conductor disposed on the at least one dielectric layer and electrically connected with the copper vias ( see FIG. 2M and [0027-0045]).
Allowable Subject Matter
Claims 3-8, 12-14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893
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