DETAILED ACTION
Claims 1-25 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (17/526,003) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 17/526,003 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
The examiner notes that applicant has cited NPL without providing relevant page numbers. While the NPL has been considered, please cite relevant page numbers for any NPL cited in the future, as required by 37 CFR 1.98(b)(5), to ensure consideration thereof.
Specification
The abstract of the disclosure is objected to because the first sentence includes redundancy. It appears that applicant could delete “parallel processing based on”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
This is a reminder that patent numbers must be provided in paragraphs 2 and 3 for related applications, when they issue.
Drawings
FIGs.3-4 fail to comply with 37 CFR 1.84(p)(3), which states that numbers, letters, and reference characters should not be placed upon hatched or shaded surfaces. Applicant may leave a blank space in the hatching or shading where the text occurs so that it appears distinct.
FIG.4 also looks a bit blurry/pixelated. The examiner recommends that applicant improve the quality.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 1, replace “processing” with --processing, the method-- to make it more clear the method, not the processing, comprises the subsequent steps.
Claim 12 is objected to because of the following informalities:
The claim appears to be grammatically incorrect. Does applicant mean that the outcome comprises an outcome of a variable compare operation, as opposed to the operation per se?
Claim 25 is objected to because of the following informalities:
Insert --and-- at the end of line 2.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “wide” in claims 1 and 24-25 is a relative term which renders the claim indefinite. The term “wide” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For instance, is 32 bits wide? Is 64 bits? Ones of ordinary skill in the art may disagree on the line separating wide and non-wide. Thus, increased clarity is necessary. For purposes of prior art examination, anything larger than 1 bit will be considered “wide”
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 16, “the bus that carries data cache traffic”. There is no previous recitation of such a bus. The examiner is also unclear what applicant may have meant because, from paragraph 78, data cache traffic is on a vertical bus, not a horizontal bus as set forth in parent claim 15. The examiner notes that claim 16 is a substantial duplicate of claim 18, and questions whether claim 16 should be canceled.
In claim 23, “the architectural cycle”. From claim 21, there may be more than one architectural cycle, so it is not clear which one cycle applicant is referring to.
All dependent claims are rejected due to their dependence on an indefinite claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 5 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to include all the limitations of the claim upon which it depends. Claim 5 sets forth that the subarray includes non-primitive mapped elements. However, the spatially adjacent mapping in each of the plurality of compute elements (claims 1 and 3-4), includes mapping the switch into a primitive operation in each of the plurality of compute elements (claim 1). Thus, if the elements are primitive mapped (claims 1 and 3-4), then it is contradictory to call them non-primitive mapped in claim 5. Applicant may cancel claim 5, amend it to be in proper dependent form, or present a sufficient showing that it complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar et al. (US 2021/0011770). Additionally, Wikipedia (“Switch statement”) is cited as extrinsic evidence showing the known operation of a switch statement.
Referring to claim 1, Prabhakar has taught a processor-implemented method for parallel processing comprising:
accessing an array of compute elements (FIG.1, 190, and FIGs.2-3), wherein each compute element within the array of compute elements is known to a compiler (see paragraphs 46-47 and note that a compiler compiles code for the array) and is coupled to its neighboring compute elements within the array of compute elements (see FIGs.2-3 and note that each element is connected to its neighbors through switches);
providing control for the compute elements on a cycle-by-cycle basis (compiled code would be executed over multiple cycles; thus, elements are controlled on a cycle-by-cycle basis), wherein control is enabled by a stream of wide control words generated by the compiler (code is mapped to the array and the array will execute different operations, thereby requiring more than 1 bit per command (to realize more than two commands, e.g. (if, else, switch (paragraph 43), arithmetic (paragraph 108), etc.));
initializing a compute element within the array of compute elements with a switch statement (from paragraph 43, an array element may execute a switch statement. A switch statement, which is a known statement in the art of programming, involves switching execution flow based on a comparison result for a variable (e.g. see Wikipedia, top of p.6, where cmp operations are used to determine a variable value and execute an appropriate path. Also, the example “Switch statement in C” on p.1 would require a similar compare operation). As such, an element is initialized with the variable on which the switch is based), wherein the switch statement is mapped into a primitive operation in the compute element (the switch statement would be encoded into a binary control word (mapped into a primitive operation) to execute on the compute element. Alternatively, or in addition, a switch is mapped to a primitive compare operation to determine a value and the corresponding path to execute (see top of p.6 of Wikipedia)), and wherein the initializing is based on a control word from the stream of control words (because the switch control word would identify some variable, the initialization according to that variable will take place);
Prabhakar has not taught initializing a plurality of compute elements with a switch statement, nor mapping the switch statement into a primitive operation in each element of the plurality of compute elements. However, this amounts to a mere duplication to perform switching more than once. Such is a routine expedient, not a patentable distinction, particularly where applicant has not demonstrated the criticality of having multiple switch statements. See MPEP 2144.04, including section (VI)(B). Here, allowing multiple compute elements to switch on a variable allows for more conditional execution and change of flow based thereon, which increases flexibility. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Prabhakar to include multiple switch statements and for initializing a plurality of compute elements with a switch statement, and mapping the switch statement into a primitive operation in each element of the plurality of compute elements.
Prabhakar, as modified, has taught executing each of the primitive operations in an architectural cycle (however long a switch primitive (e.g. the switch block as a whole, or just a portion of a switch block (e.g. a compare)) takes to execute, this length of time may be called an architectural cycle); and
returning a result for the switch statement, wherein the returning is determined by a decision variable (again, this is how a switch statement works. In the C example on p.1 of Wikipedia, the decision variable “age” is checked and a result is returned (either the value of “age” or any data used in the path selected by the switch based on “age”. Alternatively, on p.6 of Wikipedia, a successful comparison result would be returned to choose the appropriate path to execute).
Referring to claim 2, Prabhakar, as modified, has taught the method of claim 1 wherein the result is provided by one of the plurality of compute elements (again, if a switch is sent to the array, then a compute element will be providing the result).
Referring to claim 3, Prabhakar, as modified, has taught the method of claim 1 wherein the mapping in each element of the plurality of compute elements comprises a spatially adjacent mapping (from FIG.3 and paragraph 100, the group of elements 380 can be selected to execute an execution fragment (portion of code). The elements in this example are adjacent to at least one other element).
Referring to claim 4, Prabhakar, as modified, has taught the method of claim 3 wherein the spatially adjacent mapping comprises an M x N subarray of the array of compute elements (from FIG.3, the rightmost four elements in 380 form a 2x2 subarray).
Referring to claim 5, Prabhakar, as modified, has taught the method of claim 4 but has not taught wherein the M x N subarray includes non-primitive mapped compute elements. However, the duplication need not occur for every element in the array. That is, it is obvious for some elements to include a switch and other to not include a switch, so as to execute other operations (arithmetic, if-else, or otherwise (paragraphs 43 and 108)). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Prabhakar such that the M x N subarray includes non-primitive mapped compute elements (e.g. in FIG.3, the top 2 elements in 380 may not have switch statements (non-primitive mapped), but the 2 elements below may have switch statements (primitive mapped)).
Referring to claim 6, Prabhakar, as modified, has taught the method of claim 3 wherein the spatially adjacent mapping is determined at compile time by the compiler (from paragraphs 2-3 and 6, among others, the array is a CGRA, which executes compiler-mapped data flow graphs).
Claim 24 is mostly rejected for similar reasoning as claim 1. Prabhakar has further taught a computer program product embodied in a non-transitory computer readable medium for parallel processing, the computer program product comprising code which causes one or more processors (FIG.1, host 120 and processors in 190) to perform the claimed operations (everything in a computing system happens in response to software stored on a medium. This software would be stored in memory, e.g. memory 140).
Claim 25 is mostly rejected for similar reasoning as claim 1. Prabhakar has further taught a computer system (FIG.1) for parallel processing comprising: a memory which stores instructions (a memory, e.g. FIG.1, 140, stores instructions to control the system. Software must be present to control the hardware); one or more processors (FIG.1, 120 and processors in 190) coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to perform the claimed operations (again, all operations are a result of software being executed).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar in view of the examiner’s taking of Official Notice.
Referring to claim 7, Prabhakar, as modified, has taught the method of claim 1 but has not taught wherein the decision variable is loaded into the plurality of compute elements from a data cache. However, Official Notice is taken that obtaining and using a variable from data cache was well known in the art before applicant’s invention. A data cache is fast memory that caches recently accessed values to help a processor avoid having to access slower memory for that value. In addition, one of ordinary skill in the art understands that any value can be used in a switch, as this is dependent on program needs. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Prabhakar to include a data cache to allow faster access to stored values, wherein the decision variable is loaded into the plurality of compute elements from the data cache.
Claims 8-9, 11-13, and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar in view of Wikipedia.
Referring to claim 8, Prabhakar, as modified, has taught the method of claim 1 but has not taught wherein the decision variable is provided to the compute elements by the control word. However, Wikipedia has taught obtaining and using a variable from an instruction itself as part of a switch (e.g. from register “ah” at the top of p.6). A register identified by the instruction is fast storage within the processor. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Prabhakar such that the decision variable is provided to the compute elements by the control word.
Referring to claim 9, Prabhakar, as modified, has taught the method of claim 1 but has not taught updating the decision variable. However, Wikipedia has also taught such an update. For instance, see the code at the top of p.6, where the decision variable is “ah”. Assuming it matches “00h”, the code at label “a:” is executed and ah is updated with “0Eh”. One of ordinary skill in the art understands that a register could be re-used for further processing, whatever that may be. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Prabhakar to update the decision variable to allow fast storage for further processing.
Referring to claim 11, Prabhakar, as modified, has taught the method of claim 9 wherein the updating the decision variable is based on an outcome of one of the primitive operations (from the top of p.6 of Wikipedia, based on the outcome of the switch operation, ah is updated in path a or b).
Referring to claim 12, Prabhakar, as modified, has taught the method of claim 11 wherein the outcome of one of the primitive operations comprises a variable compare operation (from the top of p.6 of Wikipedia, see the cmp operation, which compares variable ah to a value).
Referring to claim 13, Prabhakar, as modified, has taught the method of claim 12 wherein the variable compare operation satisfies a case statement derived from the switch statement (from the top of p.6 of Wikipedia, the compare determines a case where the variable = 00h, a case where the variable = 01h, and a default case where the variable is something else. The case statements are part of the overall switch-case construct (e.g. see p.1 of Wikipedia, in the example C code)).
Referring to claim 19, Prabhakar, as modified, has taught the method of claim 9 wherein the updating the decision variable is based on the result that was returned (again, see the top of p.6 of Wikipedia, which shows how the decision variable ah can be updated based on the result returned by the switch comparison).
Referring to claim 20, Prabhakar, as modified, has taught the method of claim 19 wherein the result that was returned comprises successful completion of the executing (returning of a result comprises successful execution; otherwise a result would not be returned. Also, a comparison returns a result of “successful comparison (match)” or “unsuccessful comparison (mismatch)”. The former may be considered “successful completion of the executing”).
Referring to claim 21, Prabhakar, as modified, has taught the method of claim 1 but has not taught further comprising delaying the returning a result, based on at least one of the primitive operations requiring more than one architectural cycle. However, Wikipedia shows how a switch statement can be used to update variables and choose additional paths of execution at the top of p.6. Here, each operation of the switch block could be said to take an architectural cycle. Thus, if ah = 01h, then multiple architectural cycles will have already passed determining that ah does not equal 00h and that the “a” path should not be taken. Thus, the result of the “b” path is delayed. The determination of the case based on serially executing basic cmp and je instructions is a simple implementation of the switch block. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Prabhakar to delay the returning a result, based on at least one of the primitive operations requiring more than one architectural cycle.
Referring to claim 22, Prabhakar, as modified, has taught the method of claim 21 wherein the delaying is based on the decision variable (again, looking at the code at the top of p.6 of Wikipedia, the amount of delay would be based on the value of ah).
Referring to claim 23, Prabhakar, as modified, has taught the method of claim 21 wherein the decision variable is propagated within the architectural cycle (decision variable ah is propagated during the cycle the first compare primitive is executed at the top of p.6 of Wikipedia).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar in view of Wikipedia and the examiner’s taking of Official Notice.
Referring to claim 10, Prabhakar, as modified, has taught the method of claim 9 but has not taught wherein the updating the decision variable is based on a load into the array of compute elements from a data cache. However, for similar reasoning as that in the rejection of claim 7, it is obvious for a variable to come from a fast data cache. As an example, taking the code at the top of p.6 of Wikipedia, it would be obvious for the value in the ah register to have originated in cache.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar in view of Wikipedia and Kirsch (US 2004/0054870).
Referring to claim 14, Prabhakar, as modified, has taught the method of claim 9 but has not taught wherein the updating the decision variable is accomplished by broadcasting the decision variable. However, Kirsch has taught broadcasting data as one way to update a variable (e.g. see paragraph 147 and FIG.6, which shows control of individual elements to accept a broadcasted value from an edge register). This allows flexibility via updates of a variable in selective elements. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Prabhakar such that the updating the decision variable is accomplished by broadcasting the decision variable.
Referring to claim 15, Prabhakar, as modified, has taught the method of claim 14 wherein the broadcasting occurs along a horizontal bus (e.g. see FIG.6 of Kirsch, where a value ‘A’, for instance, is sent to a row of elements via a horizontal bus).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Prabhakar in view of Wikipedia, Kirsch, and the examiner’s taking of Official Notice.
Referring to claim 16, Prabhakar, as modified, has taught the method of claim 15 but has not taught wherein the mapping in each element of the plurality of compute elements is performed by the compiler to minimize broadcasting along the bus that carries data cache traffic. However, for similar reasoning given above in the rejection of claim 7, it is obvious for a data value, including a broadcasted value, to originate in a cache. In the combination of prior art, data may be quickly accessed from cache, stored in an edge register in Kirsch, and broadcasted to selected elements so as to perform a switch based on the broadcasted value. A switch operation, as shown on the top of p.6 of Wikipedia, references the same variable (ah) multiple times to determine the appropriate path. Thus, the value in ah would only need to be broadcasted once, which means broadcasting is minimized on the data cache bus.
Referring to claim 17, Prabhakar, as modified, has taught the method of claim 14 but has not taught wherein the broadcasting occurs along a bus that carries data cache traffic. However, for similar reasoning given above in the rejection of claim 7, it is obvious for a data value, including a broadcasted value, to originate in a cache.
Referring to claim 18, Prabhakar, as modified, has taught the method of claim 17 wherein the mapping in each element of the plurality of compute elements is performed by the compiler to minimize broadcasting along the bus that carries data cache traffic (as stated in the rejection of claim 16, in the combination of prior art, data may be quickly accessed from cache, stored in an edge register in Kirsch, and broadcasted to selected elements so as to perform a switch based on the broadcasted value. A switch operation, as shown on the top of p.6 of Wikipedia, references the same variable (ah) multiple times to determine the appropriate path. Thus, the value in ah would only need to be broadcasted once, which means broadcasting is minimized on the data cache bus).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Coon (8,312,254) has taught a SIMT processor (array) that has an indirect branch instruction to implement switch statements.
Hamzeh has taught “Branch-Aware Loop Mapping on CGRAs” where loops with conditional operations are mapped to an array.
Mathew (2020/0004690) has taught an array processor that performs pick and switch operations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183