DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 5, 8, 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nitta (US 2022/0418094 A1) in view of Wu (US 2012/0187550 A1).
Regarding Claim 1, Nitta (US 2022/0418094 A1) discloses a device (Fig 1-2,4-5), comprising: a printed circuit board (PCB) (10) comprising a first signal trace (21A) electrically coupled ([0037]) to a first signal via (40); and a slot ground (50) (configured to reduce signal interference ([0059,0060] structure shown can perform this function. Note that Applicant’s Specification states [0028] “A slot ground (e.g., made up of slot 222 and associated metal plating, etc.) may reduce electrical interference such as crosstalk with respect to the electrical signal traveling between electrical components on the PCB”; as the structure shown comprising a plated slotted via, 50 can perform the function of reducing signal interference) with respect to the first signal via (40)), wherein the slot ground comprises: a slot (at 52) formed in the PCB at least partially surrounding (see Fig 1) the first signal via (40); plating (see Fig 5; [0037,0058-0062]) on a wall of the slot (52), wherein the plating is electrically coupled ([0059-0060]) to a ground plane (21) of the PCB; and resin ([0058] “inside of the electric conductors 53 and 54 may be filled with a dielectric substance such as a synthetic resin”) at least partially filling the slot (52).
Nitta does not explicitly disclose a metal plating and does not disclose wherein the first signal trace extends outside the slot from the first signal via through an open portion formed in the slot.
Wu (US 2012/0187550 A1) teaches of a device (Fig 5), comprising: a printed circuit board (PCB) (510,512,520,530; [0041,0042,0047]) comprising a first signal trace (530; [0047]) electrically coupled to a first signal via (534); and a slot ground (540,542,562) configured to reduce signal interference ([0002,0006,0023]; structure shown can perform this function. Note that Applicant’s Specification states [0028] “A slot ground (e.g., made up of slot 222 and associated metal plating, etc.) may reduce electrical interference such as crosstalk with respect to the electrical signal traveling between electrical components on the PCB”; as the structure shown comprising a plated slotted via, 50 can perform the function of reducing signal interference) with respect to the first signal via (534), wherein the slot ground comprises: a slot (aperture in 510 comprising 542) formed in the PCB partially surrounding ([0024,0031-0034]; Wu teaches the semi-circular shape effectively shields and controls the direction of the electric field) the first signal via (534), wherein the first signal trace (530) extends outside the slot (542) from the first signal via through an open portion (see Fig 5B showing a c-shaped shield wall and the signal trace extends away and outside of 542,540) formed in the slot; metal plating ([0044,0076]) on a wall of the slot, wherein the metal plating is electrically coupled ([0006,0007,0029,0032,0037]) to a ground plane (520) of the PCB.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as disclosed by Nitta, comprising a metal plating and wherein the first signal trace extends outside the slot from the first signal via through an open portion formed in the slot as taught by Wu, in order to effectively better block an electrical field than a circular shaped ground, to provide an effective shield, control field strength, reduce field energy to one direction, achieve ground shielding effect and control the direction of the electric field, control impedance, solve problems related to signal integrity and provide a conductive material that can be plated (Wu, Abstract, [0024,0031-0039,0044,0046,0060,0076]). The combination of Nitta in view of Wu would provide an effective shield allowing control of shielding direction, comprising a resin at least partially filling the slot which would allow for some level of environmental protection and prevention of contamination of the slot by preventing air or moisture or unwanted materials from entering the slot. A slot filled with resin would also provide a weight saving design as opposed to a slot completely filled with metal. The combination as taught by Nitta in view of Wu would also provide commonly found materials, as well as materials having electrical conductivity.
The claim states “plating” however “plating” references a method of forming a layer and thus is interpreted as a product-by-process claim. See MPEP 2113.
Please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitations “configured to reduce signal interference” which are narrative in form have not been given any patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997)
Regarding Claim 4, Nitta in view of Wu teaches the limitations of the preceding claim and Nitta further teaches the device (Fig 1-2,4-5) of claim 1, wherein the first signal via (40) is coupled to the first signal trace (21A) by a first signal pad (interface of 40 and 21A as seen in Fig 1-2) disposed on a first intermediate (see Fig 5 showing 21 and 31 are intermediate with respect to 71,72) layer (layer about 21) of the PCB, and wherein the slot (50; note that the physical structure of the slot shape is not being claimed) extends from a top layer (50 is a slot or slit or groove at callout 50 that extends from 32 to 31) of the PCB to a second intermediate (see Fig 5 showing 21 and 31 are intermediate with respect to 71,72) layer (layer at 31) of the PCB beneath the first intermediate layer (layer 31 is below layer 21).
Regarding Claim 5, Nitta in view of Wu teaches the limitations of the preceding claim including the metal plating and Nitta further teaches the device (Fig 1-2)of claim 4, wherein the first signal via (40) extends from the top layer (layer at 32) of the PCB to the first intermediate (see Fig 5 showing 21 and 31 are intermediate with respect to 71,72) layer (layer about 21), and wherein at least an upper portion (an upper portion or region of 40; note that the claim language has not structurally limited nor defined this claimed “portion”) of the first signal via (40) between the top layer and the first intermediate (see Fig 5 showing 21 and 31 are intermediate with respect to 71,72) layer comprises the metal plating ([0037]).
Regarding Claim 8, Nitta in view of Wu teaches the limitations of the preceding claim and Wu further discloses the device (Fig 5) of claim 1, wherein the slot (542,562) substantially forms a C-shaped profile (see Fig 5).
Regarding Claim 17, Nitta discloses a printed circuit board (PCB) (Fig 1-2), comprising: a first signal trace (21A); a first signal via (40) electrically coupled ([0037]) to the first signal trace (21A); and a slot ground (50) (configured to reduce signal interference ([0059,0060] structure shown can perform this function. Note that Applicant’s Specification states [0028] “A slot ground (e.g., made up of slot 222 and associated metal plating, etc.) may reduce electrical interference such as crosstalk with respect to the electrical signal traveling between electrical components on the PCB”; as the structure shown comprising a plated slotted via, 50 can perform the function of reducing signal interference) with respect to the first signal via (40)), wherein the slot ground comprises: a slot (at 52) formed in the PCB partially surrounding (see Fig 1) the first signal via (40); plating (see Fig 5; [0037,0058-0062]) on a wall of the slot (52), wherein the plating is electrically coupled ([0059-0060]) to a ground plane (21) of the PCB; and resin ([0058] “inside of the electric conductors 53 and 54 may be filled with a dielectric substance such as a synthetic resin”) at least partially filing the slot (52).
Nitta does not explicitly disclose a metal plating and does not disclose wherein the first signal trace extends outside the slot from the first signal via through an open portion formed in the slot.
Wu (US 2012/0187550 A1) teaches of a device (Fig 5), comprising: a printed circuit board (PCB) (510,512,520,530; [0041,0042,0047]) comprising a first signal trace (530; [0047]) electrically coupled to a first signal via (534); and a slot ground (540,542,562) configured to reduce signal interference ([0002,0006,0023]; structure shown can perform this function. Note that Applicant’s Specification states [0028] “A slot ground (e.g., made up of slot 222 and associated metal plating, etc.) may reduce electrical interference such as crosstalk with respect to the electrical signal traveling between electrical components on the PCB”; as the structure shown comprising a plated slotted via, 50 can perform the function of reducing signal interference) with respect to the first signal via (534), wherein the slot ground comprises: a slot (aperture in 510 comprising 542) formed in the PCB partially surrounding ([0024,0031-0034]; Wu teaches the semi-circular shape effectively shields and controls the direction of the electric field) the first signal via (534), wherein the first signal trace (530) extends outside the slot (542) from the first signal via through an open portion (see Fig 5B showing a c-shaped shield wall and the signal trace extends away and outside of 542,540) formed in the slot; metal plating ([0044,0076]) on a wall of the slot, wherein the metal plating is electrically coupled ([0006,0007,0029,0032,0037]) to a ground plane (520) of the PCB.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Nitta, comprising a metal plating and wherein the first signal trace extends outside the slot from the first signal via through an open portion formed in the slot as taught by Wu, in order to effectively better block an electrical field than a circular shaped ground, to provide an effective shield, control field strength, reduce field energy to one direction, achieve ground shielding effect and control the direction of the electric field, control impedance, solve problems related to signal integrity and provide a conductive material that can be plated (Wu, Abstract, [0024,0031-0039,0044,0046,0060,0076]). The combination of Nitta in view of Wu would provide an effective shield allowing control of shielding direction, comprising a resin at least partially filling the slot which would allow for some level of environmental protection and prevention of contamination of the slot by preventing air or moisture or unwanted materials from entering the slot. A slot filled with resin would also provide a weight saving design as opposed to a slot completely filled with metal. The combination as taught by Nitta in view of Wu would also provide commonly found materials, as well as materials having electrical conductivity.
The claim states “plating” however “plating” references a method of forming a layer and thus is interpreted as a product-by-process claim. See MPEP 2113.
Please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitations “configured to reduce signal interference” which are narrative in form have not been given any patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997)
Regarding Claim 19, Nitta in view of Wu teaches the limitations of the preceding claim and Nitta further teaches the PCB (Fig 1-2,4-5) of claim 17, further comprising: a first signal pad (interface of 40 and 21A as seen in Fig 1-2) disposed on a first intermediate (see Fig 5 showing 21 and 31 are intermediate with respect to 71,72) layer (layer about 21) of the PCB, and wherein the slot (50; note that the physical structure of the slot shape is not being claimed) extends from a top layer (50 is a slot or slit or groove at callout 50 that extends from 32 to 31) of the PCB to a second intermediate (see Fig 5 showing 21 and 31 are intermediate with respect to 71,72) layer (layer at 31) of the PCB beneath the first intermediate layer (layer 31 is below layer 21).
Regarding Claim 20, Nitta in view of Wu teaches the limitations of the preceding claim including the metal plating and Nitta further teaches the PCB (Fig 1-2,4-5) of claim 19, wherein the first signal via (40) extends from the top layer (layer at 32) of the PCB to the first intermediate (see Fig 5 showing 21 and 31 are intermediate with respect to 71,72) layer (layer about 21), and wherein at least an upper portion (an upper portion or region of 40; note that the claim language has not structurally limited nor defined this claimed “portion”) of the first signal via (40) between the top layer and the first intermediate (see Fig 5 showing 21 and 31 are intermediate with respect to 71,72) layer comprises the metal plating ([0037]).
Claim(s) 2 – 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nitta (US 2022/0418094 A1) in view of Wu (US 2012/0187550 A1) as applied to claims 1 and 17 above and further in view of Nakamura (US 2005/0247482 A1).
Regarding Claim 2, Nitta in view of Wu teaches the limitations of the preceding claim.
Nitta does not explicitly disclose the device of claim 1, wherein a central axis of the slot is substantially coaxial with a central axis of the first signal via.
Nakamura (US 2005/0247482 A1) teaches of a device (Fig 10-11) wherein a central axis (at O1 in Fig 11) of an elongated shielding structure (44) formed within a slot-like shaped region (area of 42 comprising 44 would be a slot-shaped aperture through 42) is substantially coaxial with a central axis (O1) of a first signal via (46).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device with slot as taught by Nitta in view of Wu, wherein a central axis of the slot is substantially coaxial with a central axis of the first signal via as taught by Nakamura, in order to reducing angle differences between the via and shielding part, reduce distance between the shielding part and via, heighten stability against external noise, perform high speed transmission of differential signals, heighten reliability of signals, provide strengthened stability against external noise, and provide multiplexing (Nakamura, [0011-0023]).
Regarding Claim 3, Nitta in view of Wu teaches the limitations of the preceding claim.
Nitta does not disclose the device of claim 1, wherein the PCB further comprises a second signal trace electrically coupled to a second signal via, and wherein the slot at least partially surrounds the first signal via and the second signal via.
Nakamura (US 2005/0247482 A1) teaches of a device (Fig 10-11), wherein a PCB further comprises a second signal trace (72) electrically coupled to a second signal via (64), and wherein a shielding structure (44) formed within a slot-like shaped region (area of 42 comprising 44 would be a slot-shaped aperture through 42)at least partially surrounds a first signal via (62) and the second signal via (64).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device with slot as taught by Nitta in view of Wu, wherein the PCB further comprises a second signal trace electrically coupled to a second signal via, and wherein the slot at least partially surrounds the first signal via and the second signal via as taught by Nakamura, in order to provide high speed transmission of differential signals, and provide multiplexing (Nakamura, [0001-0023]).
Regarding Claim 18, Nitta in view of Wu teaches the limitations of the preceding claim.
Nitta does not disclose the PCB of claim 17, further comprising: a second signal trace; and a second signal via electrically coupled to the second signal trace, wherein the slot at least partially surrounds the first signal via and the second signal via.
Nakamura (US 2005/0247482 A1) teaches of a device (Fig 10-11), wherein a PCB further comprises a second signal trace (72) electrically coupled to a second signal via (64), and wherein a shielding structure (44) formed within a slot-like shaped region (area of 42 comprising 44 would be a slot-shaped aperture through 42)at least partially surrounds a first signal via (62) and the second signal via (64).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device with slot as taught by Nitta in view of Wu, further comprising: a second signal trace; and a second signal via electrically coupled to the second signal trace, wherein the slot at least partially surrounds the first signal via and the second signal via as taught by Nakamura, in order to provide high speed transmission of differential signals, and provide multiplexing (Nakamura, [0001-0023]).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta (US 2022/0418094 A1) in view of Wu (US 2012/0187550 A1) as applied to claim 5 above and further in view of Twarog (US 10,470,311 B2).
Regarding Claim 6, Nitta in view of Wu teaches the limitations of the preceding claim.
Nitta does not disclose the device of claim 5, wherein the first signal via further extends from the first intermediate layer to a bottom layer of the PCB, and wherein a lower portion of the first signal via between the first intermediate layer and the bottom layer lacks the metal plating.
Twarog (US 10,470,311 B2) teaches of a device (Fig 2), wherein a first signal via (204) further extends from a first intermediate layer (L10) to a bottom layer (LN) of the PCB, and wherein a lower portion (at 220) of the first signal via (204) between the first intermediate layer and the bottom layer lacks (through back-drilling) the metal plating (Column 2, line 60-Column 3, line 62).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device with slot and metal plating as taught by Nitta in view of Wu, wherein the first signal via further extends from the first intermediate layer to a bottom layer of the PCB, and wherein a lower portion of the first signal via between the first intermediate layer and the bottom layer lacks the metal plating as taught by Twarog, in order to remove unwanted stubs that could create unwanted signal integrity disturbances or resonance or limit performance, while still allowing for signal circuit density by allowing conductive pathways on desired layers for connecting components (Twarog, Column 2, lines 25-58).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta (US 2022/0418094 A1) in view of Wu (US 2012/0187550 A1) as applied to claim 5 above and further in view of Baek (US 2005/0146390 A1).
Regarding Claim 7, Nitta in view of Wu teaches the limitations of the preceding claim.
Nitta does not disclose the device of claim 5, wherein the first signal via intersects one or more non-functional pads disposed on one or more third intermediate layers of the PCB between the top layer and the first intermediate layer.
Baek (US 2005/0146390 A1) teaches of a device (Fig 2), wherein a first signal via (32) intersects one or more non-functional pads (51) disposed on one or more third intermediate layers of the PCB between a top layer (at 43) and a first intermediate layer (at layer above 47).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device with slot and metal plating as taught by Nitta in view of Wu, wherein the first signal via intersects one or more non-functional pads disposed on one or more third intermediate layers of the PCB between the top layer and the first intermediate layer as taught by Baek, in order to reduce impedance mismatching caused by inductance, reduce interference, adjust the distance from the signal via to the surrounding ground, and to adjust capacitance (Baek, [0005-0025]).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Nitta (US 2022/0418094 A1) in view of Wu (US 2012/0187550 A1) as applied to claim 1 above and further in view of Pritchard (US 2022/0369452 A1).
Regarding Claim 9, Nitta in view of Wu teaches the limitations of the preceding claim.
Nitta does not explicitly disclose the device of claim 1, further comprising one or more electrical components electrically coupled to the PCB.
Pritchard (US 2022/0369452 A1) teaches of a device (Fig 1-4) comprising one or more electrical components (Fig 1; [0003,0023,0025,0029,0031]) electrically coupled ([0003,0021,0023,0025,0029,0031]) to a PCB (200).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device with slot and metal plating as taught by Nitta in view of Wu, further comprising one or more electrical components electrically coupled to the PCB as taught by Pritchard, in order to provide a board for making up an information handling system, motherboard, or network interface card, allow for physical and electrical support of electronic components by the device and provide electrical connection of resources as part of a system (Pritchard, [0003,0023,0025,0029,0031]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896