Prosecution Insights
Last updated: October 24, 2026
Application No. 18/391,015

BOTTOM-UP DIELECTRIC GAP-FILL FOR DEVICE ISOLATION DURING SOURCE/DRAIN EPITAXY IN CFET

Final Rejection §102
Filed
Dec 20, 2023
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
586 granted / 686 resolved
+17.4% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
723
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
42.2%
+2.2% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 686 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Amendment filed 9/9/2026. Claims 1-11 are pending. Claims 1-6 are withdrawn. Claim 12 is cancelled. Claim 7 is currently amended. Claim 7 is independent. Response to Arguments Applicants’ arguments and amendments, filed 9/9/2026, with respect to Drawings Objections and 112 Rejections, as indicated in line numbers 2-4 of the office action mailed 5/15/2026, have been fully considered and are persuasive. The objections and rejections have been withdrawn. Applicants' arguments and amendments, filed 9/9/2026, with respect to independent claim 7, although substantive and pertinent to expediting the prosecution of the current application, are considered moot and not persuasive, respectfully, in light of new grounds of rejections made using the prior arts of Lin and Reboh as noted below in the rejections of independent claim 7. A. Prior-art rejections based at least in part by Lin Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 7-9 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 2024/0072136 A1, hereinafter “Lin”). Regarding independent claim 7, Figure 1Q of Lin discloses a gate all around (GAA) complementary field effect transistor (CFET) device circuit, comprising: a plurality of adjacent epitaxy layers 108A (“semiconductor layers… epitaxial growth”- ¶¶0023, 0025), fabricated such that each of the plurality of epitaxy layers 108A are separated by a source/drain (S/D) canyon 502 (“source/drain trenches”- ¶0033; see Fig. 1F for notation), each canyon 502 defined by a sidewall of a first GAA CFET (i.e., the CFET corresponding to gate 1506-1), and a sidewall of a second GAA CFET (i.e., the CFET corresponding to gate 1506-2); a spacer cover 1302 (“layers”- ¶0045) deposited on the sidewall of the first GAA CFET, and on the sidewall of the second GAA CFET; and an isolator 1304 (“interlayer dielectric (ILD) layer”- ¶0046) deposited in a void (i.e., the space previously occupied by 1204, which is removed and then filled in by 1304- ¶0046) at a target depth height, wherein the void is created by etching away a dummy fill 124 (“polymer layers”- ¶0046) previously deposited in the S/D canyon 502 based on the target depth height. Additionally, regarding the claim limitation “wherein the void is created by etching away a dummy fill previously deposited in the S/D canyon based on the target depth height” which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same. Regarding claim 8, Figure 1Q of Lin discloses the circuit further comprising: an NP dielectric 902 (“dielectric layers”- ¶0037) disposed between a first device 5000P (“PFET”- ¶0026) having a first polarity and a second device 5000N (“NFET”- ¶0026) having a second, opposite polarity (¶0026). Regarding claim 9, Figure 1Q of Lin discloses wherein the first device 5000P comprises the plurality of adjacent epitaxy layers 108A, and the second device 5000N comprises a second plurality of adjacent epitaxy layers 108C (“semiconductor layers… epitaxial growth”- ¶¶0023, 0025) disposed over the NP dielectric 902. Regarding claim 11, Figure 1Q of Lin discloses wherein the NP dielectric 902 occupies an NP void 802 (“gap”- ¶0036; see Fig. 1l for notation) formed by removal of an NP dummy filler 106B (“layer”- ¶0036). Additionally, regarding the claim limitation “an NP void formed by removal of an NP dummy filler” which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same. B. Prior-art rejections based at least in part by Reboh Claim Rejections - 35 USC § 102 Claims 7-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Reboh et al. (US 2025/0203935 A1, hereinafter “Reboh”). Regarding independent claim 7, Figure 10A of Reboh discloses a gate all around (GAA) complementary field effect transistor (CFET) device circuit, comprising: a plurality of adjacent epitaxy layers 12A (“channels… epitaxy”- ¶0043), fabricated such that each of the plurality of epitaxy layers 12A are separated by a source/drain (S/D) canyon (i.e., the space occupied by source/drain 162A, 162B and 61, 71 and 92B), each canyon defined by a sidewall of a first GAA CFET (i.e., the CFET corresponding to left gates 176A, 176B as shown in Fig. 10A), and a sidewall of a second GAA CFET (i.e., the CFET corresponding to middle gates 176A, 176B as shown in Fig. 10A); a spacer cover 71 (”ILD”- ¶0055) deposited on the sidewall of the first GAA CFET, and on the sidewall of the second GAA CFET; and an isolator 61 (“dielectric isolation”- ¶0051) deposited in a void (i.e., the space occupied by 61) at a target depth height. Additionally, regarding the claim limitation “wherein the void is created by etching away a dummy fill previously deposited in the S/D canyon based on the target depth height” which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same. Regarding claim 8, Figure 10A of Reboh discloses the circuit further comprising: an NP dielectric 41 (“dielectric isolation”- ¶0047) disposed between a first device 1200 (“GAA FET”- ¶0075) having a first polarity and a second device 1201 (“GAA FET”- ¶0075) having a second, opposite polarity (¶¶0043, 0050). Regarding claim 9, Figure 10A of Reboh discloses wherein the first device 1200 comprises the plurality of adjacent epitaxy layers 12A, and the second device 1201 comprises a second plurality of adjacent epitaxy layers 12B (“channels… epitaxy”- ¶0043) disposed over the NP dielectric 41. Regarding claim 10, Figure 10A of Reboh discloses wherein the second plurality of adjacent epitaxy layers 12B include a polarity which is opposite to a polarity of the adjacent epitaxy layers 12A (¶0043). Regarding claim 11, Figure 10A of Reboh discloses wherein the NP dielectric 41 occupies an NP void (i.e., the space occupied by 41). Additionally, regarding the claim limitation “an NP void formed by removal of an NP dummy filler” which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/ Primary Examiner, Art Unit 2817
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Prosecution Timeline

Dec 20, 2023
Application Filed
May 15, 2026
Non-Final Rejection mailed — §102
May 27, 2026
Applicant Interview (Telephonic)
May 29, 2026
Examiner Interview Summary
Sep 09, 2026
Response Filed
Oct 06, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+13.9%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 686 resolved cases by this examiner. Grant probability derived from career allowance rate.

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