Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: AMAT P2692
Filling Date: 12/20/23
Inventor: Breil et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-7, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 2022/0406664 A1) in view of Khaderbad et al (US 2022/0165732 A1).
Regarding claim 1, Xie discloses a method for fabricating a gate all-around (GAA) field effect transistor, FET (see paragraph [0001] “field effect transistor (FET)”; and see paragraph [0043] “in a gate-all-around (GAA) arrangement”), comprising: forming a plurality of epitaxy layers on a substrate (see paragraph [0029]. “In order to form the nanosheet channel layers 108, an epitaxy stack (not shown) is first grown on the substrate 102 using known epitaxial growth processes. The epitaxy stack includes alternating sacrificial layers 106 and nanosheet channel layers 108”), wherein a formed epitaxy layer includes a plurality of doped channels (nanosheet channel layers 108) (see paragraph [0005]. “The one or more nanosheet field-effect transistors formed on the first portion or the second portion of the substrate may be a p-type nanosheet field-effect transistors”; and see paragraph [0029]. “The nanosheet channel layers 108 may be made of silicon”), a plurality of metal channels (see paragraph [0043] “Portions of the metal gate stacks 136, within the structure 100, are formed in the spaces 134 (illustrated in Fig. 6 ) formerly occupied by the removed sacrificial layers 106… The metal gate stacks 136 may further include work function metals (such as TiN, TiAl, TiAlC, TaN, etc.) and low resistance metal fills (such as Al, W, Co, Ru, etc.)”), and a dummy gate (the portion of the epitaxy stack that is under gate spacers 114 - see Figs. 1 and 13; note this designation is in accordance with the definition of dummy gate given in paragraph [0024] of the current application); partially etching a plurality of layers to create a plurality of voids; depositing an inner spacer (inner spacer 116) in each void of the plurality of voids (see paragraph [0033]. “Further, using a dry or wet isotropic etching process, the sacrificial layers 106 are then laterally recessed, selective to the nanosheet channel layers 108. Since the nanosheet channel layers 108 are not recessed, the lateral recessing of the sacrificial layers 106 forms indents between these nanosheet channel layers 108. The indents extend laterally the width of the gate spacer 114 (i.e., the indents extend laterally from the inner sidewall to the outer sidewall of the gate spacer 114). The indents are then filled by pinch-off mechanism, using a deposition process such as ALD, with a dielectric material, such as silicon nitride or any other low-k dielectric material, to form the inner spacers 116”); depositing a spacer (gate spacer 114) in a source/drain cavity, wherein at least a portion of the spacer is deposited on a dummy gate of a formed epitaxy layer (see Figs. 1 and 13); and depositing a stressed metal filler (metal contact 146) in the source/drain cavity (see paragraph [0054] “That is, the metal contacts 146 within the pFET portion of the structure 200 fill the space between the inner sidewalls of the third source drain epitaxy 144. As a result, the metal contacts 146 vertically extend to the bottom most nanosheet channel layer 108”; and see paragraph [0055]. “Typically, materials used to form the metal contacts 146 may transfer a substantial amount of stress”).
Xie discloses that sacrificial layers 106 are partially etched to create a plurality of voids and that an inner spacer is deposited in each void of the plurality of voids as described in paragraph [0033] and quoted above. The sacrificial layers 106 are not described as being made of metal at the time the etching is performed. Instead, the etching is performed prior to having portions of the metal gate stacks formed in the spaces 134 formerly occupied by the removed sacrificial layers as described in paragraph [0043] and quoted above.
However, Xie does not disclose partially etching the plurality of metal channels.
However, Khaderbad is also relates to GAA FETS (see paragraphs [0016], [0024] and [0025]) discloses partially etching a plurality of metal channels to create a plurality of voids and that an inner spacer is deposited in each void of such plurality of voids created by the partial etching of the plurality of metal channels (in Khaderbad, see Fig. 12; see paragraph [0021] “operations 102 and 104 are performed repeatedly to form two or more pairs of the sacrificial channel layer 14 and the channels stack 22”; see paragraph [0023] “The sacrificial channel layer 14 includes a metal”; and see paragraph [0063]. The inner spacers 60 may be formed by selectively etching the sacrificial channel layers 14 to form spacer cavities between the channel stacks 22, forming an insulating layer by a blanket deposition, then etching back the insulating layer to leave the insulating layer in the spacer cavities as the inner spacers 60”).
Each of Xie and Khaderbad relates to GAA FETS. In view of the disclosure of Khaderbad, it would have been obvious to a person of ordinary skill in the art to modify the method of Xie by substituting metal as the sacrificial material in the sacrificial layers 106 of Xie, such that the partial etching would be of modified metal layers/channels 106, in order that the modified metal layers/channels 106 and the base layer would be more selectively removable with respect to one another than in the unmodified method of Xie, see paragraph [0029] of Xie.
Regarding claim 6, Xie discloses a gate all-around (GAA) field effect transistor, FET (see paragraph [0001] “field effect transistor (FET)”; and see paragraph [0043] “in a gate-all-around (GAA) arrangement”), comprising: a plurality of epitaxy layers on a substrate (see paragraph [0029]. In order to form the nanosheet channel layers 108, an epitaxy stack (not shown) is first grown on the substrate 102 using known epitaxial growth processes. The epitaxy stack includes alternating sacrificial layers 106 and nanosheet channel layers 108”), wherein a formed epitaxy layer includes a plurality of doped channels (nanosheet channel layers 108) (see paragraph [0005]. “The one or more nanosheet field-effect transistors formed on the first portion or the second portion of the substrate may be a p-type nanosheet field-effect transistors”; and see paragraph [0029] “The nanosheet channel layers 108 may be made of silicon”), a plurality of metal channels (see paragraph [0043] “portions of the metal gate stacks 136, within the structure 100, are formed in the spaces 134 (illustrated in Fig. 6 ) formerly occupied by the removed sacrificial layers 106. The metal gate stacks 136 may further include work function metals (such as TiN, TiAl, TiAlC, TaN, etc.) and low resistance metal fills (such as Al, W, Co, Ru, etc.)”), and a dummy gate (the portion of the epitaxy stack that is under gate spacers 114 - see Figs. 1 and 13; note this designation is in accordance with the definition of dummy gate given in paragraph [0024] of the current application); partially etching a plurality of layers to create a plurality of voids; depositing an inner spacer (inner spacer 116) in each void of the plurality of voids (see paragraph [0033] “Further, using a dry or wet isotropic etching process, the sacrificial layers 106 are then laterally recessed, selective to the nanosheet channel layers 108. Since the nanosheet channel layers 108 are not recessed, the lateral recessing of the sacrificial layers 106 forms indents between these nanosheet channel layers 108. The indents extend laterally the width of the gate spacer 114 (i.e., the indents extend laterally from the inner sidewall to the outer sidewall of the gate spacer 114). The indents are then filled by pinch-off mechanism, using a deposition process such as ALD, with a dielectric material, such as silicon nitride or any other low-k dielectric material, to form the inner spacers 116”); depositing a spacer (gate spacer 114) in a source/drain cavity, wherein at least a portion of the spacer is deposited on a dummy gate of a formed epitaxy layer (see Figs. 1 and 13); and depositing a stressed metal filler (metal contact 146) in the source/drain cavity (see paragraph [0054]. “That is, the metal contacts 146 within the pFET portion of the structure 200 fill the space between the inner sidewalls of the third source drain epitaxy 144. As a result, the metal contacts 146 vertically extend to the bottom most nanosheet channel layer 108”; and see paragraph [0055] “Typically, materials used to form the metal contacts 146 may transfer a substantial amount of stress”).
Xie discloses that sacrificial layers 106 are partially etched to create a plurality of voids and that an inner spacer is deposited in each void of the plurality of voids as described in paragraph [0033] and quoted above. The sacrificial layers 106 are not described as being made of metal at the time the etching is performed. Instead, the etching is performed prior to having portions of the metal gate stacks formed in the spaces 134 formerly occupied by the removed sacrificial layers as described in paragraph [0043] and quoted above.
Therefore, Xie does not disclose partially etching the plurality of metal channels.
However, Khaderbad is also relates to GAA FETS (see paragraphs [0016], [0024] and [0025]) discloses partially etching a plurality of metal channels to create a plurality of voids and that an inner spacer is deposited in each void of such plurality of voids created by the partial etching of the plurality of metal channels (in Khaderbad, see Fig. 12; see paragraph [0021]. “Operations 102 and 104 are performed repeatedly to form two or more pairs of the sacrificial channel layer 14 and the channels stack 22”; see paragraph [0023]. “The sacrificial channel layer 14 may include a metal”; and see paragraph [0063]. “The inner spacers 60 may be formed by selectively etching the sacrificial channel layers 14 to form spacer cavities between the channel stacks 22, forming an insulating layer by a blanket deposition, then etching back the insulating layer to leave the insulating layer in the spacer cavities as the inner spacers 60”).
Each of Xie and Khaderbad relates to GAA FETS. In view of the disclosure of Khaderbad, it would have been obvious to a person of ordinary skill in the art to modify the method of Xie by substituting metal as the sacrificial material in the sacrificial layers 106 of Xie, such that the partial etching would be of modified metal layers/channels 106, in order that the modified metal layers/channels 106 and the base layer would be more selectively removable with respect to one another than in the unmodified method of Xie, see paragraph [0029] of Xie.
Regarding claims 2 and 7, Khaderbad discloses that forming a plurality of epitaxy layers further comprises: depositing a plurality of layers including a plurality of doped channels and a plurality of metal channels; and etching the plurality of layers to isolate a first plurality of epitaxy layers (fin structure 28) from a second plurality of epitaxy layers (fin structure 29) (see Figs. 31 and 32; see paragraph [0104] “In the embodiment shown FIGS. 31 to 34, the pFET is formed using operation similar to the embodiment described in FIGS. 2-11. However, other embodiments, such as the embodiments described in FIGS. 12-29, alone or in combination, may also be used”; see paragraph [0108]. “In operation 204, a semiconductor film stack 17 for n-type device is formed… The semiconductor film stack 17 includes alternating semiconductor layers made of different materials to facilitate formation of nanosheet channels in a multi-gate n-type device, such as nanosheet channel nFETs”; and see paragraph [0112]. “In operation 206, fin structures 28, 29 are formed using one or more patterning and etching processes, as shown in FIG. 32. In some embodiments, the fin structures 28, 29 may be formed using separate etching process. In other embodiments, the fin structures 28, 29 are formed using the same etching process”).
Regarding claims 3 and 9, Xie discloses depositing the stressed metal filler to include compressive stress (see paragraph [0054] “The metal contacts 146 may be composed of metal, such as tungsten or cobalt”; and see paragraph [0055]. “Typically, materials used to form the metal contacts 146 may transfer a substantial amount of stress to the nanosheet channel layers 108. For the nanosheet pFET (i.e., pFET portion of the structures 100, 200), compressive stress is most beneficial because compressive stress is beneficial for higher hole mobility. This allows for the integrated circuit to work more efficiently. The compressive stress may be achieved with the resultant structure 200, illustrated in FIG. 13”).
Regarding claims 4 and 10, Xie discloses that the method further comprises: depositing a dummy polygate (sacrificial gate 110) on the epitaxy layer (see paragraph [0030] “The sacrificial gates 110 may be formed by first depositing a sacrificial gate material, such as, for example, a thin layer of SiO2 followed by…polycrystalline silicon (polysilicon) on top of structure 100”); depositing a hard mask (hard mask cap 112) on the dummy polygate (see paragraph [0030]. “The sacrificial gates 110 are covered by a hard mask cap 112”); and further depositing the spacer on the hard mask, such that the spacer insulates the stressed metal filler from: an epitaxy layer, the dummy polygate, and the hard mask (see paragraph [0032]. “The gate spacer 114 is formed at the sidewalls of the sacrificial gates 110 and cover the hard mask caps 112”).
Claim(s) 5, 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 2022/0406664 A1) in view of Khaderbad et al (US 2022/0165732 A1) and further in view of Clifton et al (US 2009/0104746 A1).
Regarding claims 5 and 11, Xie and Khaderbad fail to disclose that the method further comprises fabricating a complementary FET. However Clifton discloses fabricating a complementary GAA FET (see paragraph [0023]. “A further special case of the present process is a complementary process, with both n-channel and p-channel FETs created”; and see paragraph [0028]. “A special class of FET for which the present technology may also be particularly advantageous is thin-body devices, in which the channel is formed in a relatively thin semiconductor layer, for example, a semiconductor wire (for example, a “gate all-around FET”) including a first epitaxy layer and a second epitaxy layer; and depositing a first stressed metal filler corresponding to the first epitaxy layer, and a second stressed metal filler corresponding to the second epitaxy layer (see Fig. 2; see paragraph [0005]. “In various embodiments, the present invention provides a process for forming a FET (e.g., an n-FET or a p-FET) such that during the formation process, a metal which makes up a source or drain of the transistor is stressed”; see paragraph [0015]. “An example of a metal which may serve as a FET source or drain is LaB6”; and see paragraph [0023] “A further special case of the present process is a complementary process, with both n-channel and p-channel FETs created. For example, n-channel FETs (n-FETs) may be formed with a metal under a state of tensile strain, for example with a relatively low workfunction, while p-channel FETs (p-FETs) may be formed with a metal under a state of compressive strain, for example with a relatively high workfunction, with channel regions comprising silicon”)
Xie, Khaderbad and Clifton, each relates to GAA FETs. In view of the disclosure of D3, it would have been obvious to a person of ordinary skill in the art to modify a method embodying a combination of the methods of Xie and Khaderbad, by fabricating a complementary GAA FET including a first epitaxy layer and a second epitaxy layer, and depositing a first stressed metal filler corresponding to the first epitaxy layer, and a second stressed metal filler corresponding to the second epitaxy layer, in order to obtain a more complex version of a GAA FET.
Regarding claim 8, Xie and Khaderbad fail to disclose that the stressed metal filler is deposited to include a tensile stress. However, Clifton discloses a stressed metal filler deposited to include a tensile stress (see paragraph [0023]. “For example, n-channel FETs (n-FETs) may be formed with a metal under a state of tensile strain, for example with a relatively low workfunction. This would allow for longitudinal tensile stress the n-FET channels, beneficial to carrier transport in the respective device in the case of silicon channels”.
Claim(s) 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 2022/0406664 A1) in view of Khaderbad et al (US 2022/0165732 A1) and further in view of Lilak et al (US 2020/0098756 A1).
Regarding claims 5 and 11, Xie and Khaderbad fail to disclose that the method further comprises fabricating a complementary FET. However, Lilak discloses a method that comprises fabricating a complementary GAA FET (see paragraph [0032]. Further still, in some embodiments, the techniques described herein can be used to form complementary transistor circuits (such as CMOS circuits), where the techniques can be used to benefit one or more of the included n-channel and p-channel transistors making up the CMOS circuit. Further yet, in some embodiments, the techniques described herein can be used to benefit a multitude of transistor configurations, such as, gate-all-around (GAA) configurations (e.g., nanowire or nanoribbon)”), including a first epitaxy layer and a second epitaxy layer (see Fig. 7; and see paragraph [0064]. “In one embodiment, alternating blanket layers of sacrificial material 136 and channel material 138 can be formed using layer-by-layer epitaxial growth, where the sacrificial material 136 can subsequently be removed to release nanowires, nanoribbons, or nanosheets of the channel material 138”, it is asserted that the recited first epitaxy layer corresponds to upper device section 106 in Fig. 7 and the recited second epitaxy layer corresponds to lower device section 108 in Fig. 7, or vice versa), and depositing a first stressed metal filler, work function layer 145 in upper or lower device section corresponding to the first epitaxy layer, and a second stressed metal filler (work function layer 145 in lower or upper device section) corresponding to the second epitaxy layer
(see, Fig. 4B; and see paragraph [0044]. “Using these techniques in a stacked transistor configuration enables independent optimization of lattice strain in NMOS devices and PMOS devices, as will be appreciated”).
Xie, Khaderbad and Lilak each relates to GAA FETS. In view of Lilak, it would have been obvious to a person of ordinary skill in the art to modify a method embodying a combination of the methods of Xie and Khaderbad by fabricating a complementary GAA FET including a first epitaxy layer and a second epitaxy layer, and depositing a first stressed metal filler corresponding to the first epitaxy layer, and a second stressed metal filler corresponding to the second epitaxy layer, in order to obtain a more complex version of a GAA FET (Fig. 7).
Conclusion
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817