DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on January 22, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner except as otherwise indicated.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-3, 8-11, 16, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ku (US 2012/0270395 A1).
Regarding claim 1, Ku discloses a method for fabricating semiconductor devices comprising:
sequentially forming a first hardmask layer (Fig. 2A 15; [0022]) and a second hardmask layer (Fig. 2A 16; [0022]) over a metallic layer (Fig. 2A 12; [0022]);
patterning the second hardmask layer (Fig. 2E 16A; [0035]) and then the first hardmask layer (Fig. 2F 15A; [0038]);
oxidizing a sidewall (Fig. 2G 22; [0043]) of the patterned first hardmask layer (15A);
removing the oxidized sidewall ([0049]) of the first hardmask layer (15A);
and etching the metallic layer (Ku Fig. 2H 12; [0047 and 0049]) using a remaining portion of the first hardmask layer (15A) as a mask (during the removing-and-etching process, the metallic layer 12 is etched using a remaining portion of layer 15A as the etching process progresses, i.e., even though layer 15A maybe completely removed at the end of the etch in Fig. 2H, the metallic layer 12 was etched using a remaining portion of the layer 15A at some point during the etching process).
Regarding claim 2, Ku discloses the method of claim 1, wherein the step of removing the oxidized sidewall (22, [0049]) of the first hardmask layer (15A) comprises flowing an etchant gas ([0047]).
Regarding claim 3, Ku discloses the method of claim 1, wherein the step of removing the oxidized sidewall (22, [0049]) of the first hardmask layer (15A) is ion-free ([0047]).
Ion-free has been interpreted to mean any etchant that has not been ionized up to the etching process.
Regarding claim 8, Ku discloses the method of claim 1, wherein the method further comprises: prior to forming the first hardmask layer (15), covering the metallic layer (12) with a third hardmask layer (Fig. 2A 14) comprising an organic dielectric ([0022]).
Regarding claim 9, Ku disclose the method of claim 1, wherein the remaining portion of the first hardmask layer (15A) has a first dimension and the patterned second hardmask layer (16A) has a second dimension, and wherein the first dimension is smaller than the second dimension (i.e., in Figs. 2G-2H, as the etching process for etching the metallic layer 12 progresses, there is a point in time when a vertical/critical dimension of layer 16A becomes smaller than a vertical/critical dimension of layer 15A).
Regarding claim 10, Ku discloses a method for fabricating semiconductor devices, comprising:
forming a first hardmask layer (15) over a metallic layer (12);
forming a second hardmask layer (16) over the first hardmask layer (15);
performing a first etching process ([0038]) to pattern the first hardmask layer (15A) through the second hardmask layer (16A), thereby exposing a sidewall of the patterned first hardmask layer (15A);
removing a portion of the exposed sidewall (Fig. 2H and [0049]) of the first hardmask layer (15A) through flowing an ion-free etchant gas ([0047], i.e., even if layer 15A were completely removed at the end of the etch, the exposed sidewall of layer 15A is removed during the etching process);
and performing a second etching process ( [0047 and 0049]) using a remaining portion of the first hardmask layer (15A) as a mask to pattern the metallic layer (Ku Fig. 2H 12; [0047 and 0049], during the removing-and-etching process, the metallic layer 12 is etched using a remaining portion of layer 15A as the etching process progresses, i.e., even though layer 15A maybe completely removed at the end of the etch in Fig. 2H, the metallic layer 12 was etched using a remaining portion of the layer 15A at some point during the etching process).
Ion-free etchant gas has been interpreted to mean any gas that has not been ionized up to the etching process.
Regarding claim 11, Ku discloses the method of claim 11, wherein the removed portion of the exposed sidewall comprises an oxidized dielectric material (22, [0043]).
Regarding claim 16, Ku discloses the method of claim 10, further comprising: prior to forming the first hardmask layer (15), covering the metallic layer (12) with a third hardmask layer (14) comprising an organic dielectric ([0022]).
Regarding claim 18, Ku discloses a method for fabricating semiconductor devices, comprising:
forming a first hardmask layer (15) over a metallic layer (12);
forming a second hardmask layer (16) over the first hardmask layer (15);
performing a first etching process (Figs. 2E-2F and [0038]) to pattern the first hardmask layer (15A) through the second hardmask layer (16A);
oxidizing a sidewall (22; [0043]) of the patterned first hardmask layer (15A);
removing the oxidized sidewall (22, [0049]) of the first hardmask layer (15A) through flowing an ion-free etchant gas ([0047]);
and performing a second etching process (Fig. 2H and [0049]) using a remaining portion of the first hardmask layer (15A) as a mask to pattern the metallic layer (12, during the removing-and-etching process, the metallic layer 12 is etched using a remaining portion of layer 15A as the etching process progresses, i.e., even though layer 15A maybe completely removed at the end of the etch in Fig. 2H, the metallic layer 12 was etched using a remaining portion of the layer 15A at some point during the etching process).
Regarding claim 20, Ku disclose the method of claim 18, wherein the remaining portion of the first hardmask layer (15A) has a first dimension and the patterned second hardmask layer (16A) has a second dimension, and wherein the first dimension is smaller than the second dimension (i.e., in Figs. 2G-GH, as the etching process for etching the metallic layer 12 progresses, there is a point in time when a vertical/critical dimension of layer 16A becomes smaller than a vertical/critical dimension of layer 15A).
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[AltContent: textbox (For the record, the inserted figure (annotated Fig. 7 of Bouche) depicts the etching of the sidewall (14S) of the first hardmask (14) below the second hardmask (16) as a pattern, where the length of second hardmask (L2) is greater than the length than the first hardmask (L1).)]5. Claims 10-11 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bouche (US 10,229,850 B1).
Regarding claim 10, Bouche discloses a method for fabricating semiconductor devices, comprising:
forming a first hardmask layer (Fig. 1 14; Col. 2 Rows 21-23) over a metallic layer (Bouche Fig. 1 12; Col. 2 Rows 21-23);
forming a second hardmask layer (Fig. 1 16; Col. 2 Rows 21-23) over the first hardmask layer (14);
performing a first etching process (Figs. 5-6; Col. 4 Rows 10-11) to pattern the first hardmask layer (14) through the second hardmask layer (16), thereby exposing a sidewall (annotated Fig. 7 14S) of the patterned first hardmask layer (14);
removing (Col. 4 Rows 41-42) a portion of the exposed sidewall (annotated Fig 7 14S, see inserted figure above) of the first hardmask layer (14) through flowing an ion-free etchant gas (Col. 4 Rows 48-50);
and performing a second etching process (Figs. 7-8; Col. 5 Rows 10-12) using a remaining portion of the first hardmask layer (14) as a mask to pattern the metallic layer (12).
Bouche discloses using reactive ion etching despite not explicitly disclosing an ion-free etchant gas. One having ordinary skill in the art before the effective filing date would know reactive ion etching utilizes gas to selectively etch layers as evidenced by Chen et al (US 2022/0320309 A1, hereafter Chen) (Chen [0058]).
Regarding claim 11, Bouche discloses the method of claim 10, wherein the removed portion of the exposed sidewall (14S) comprises an oxidized dielectric material (Col. 2 Rows 31-32).
Regarding claim 17, Bouche discloses the method of claim 10, wherein the remaining portion of the first hardmask layer (14) has a first dimension (annotated Bouche Fig. 7 L1) and the patterned second hardmask layer (16) has a second dimension (annotated Bouche Fig. 7 L2), and wherein the first dimension (L1) is smaller than the second dimension (L2) (Bouche Fig. 7; Col. 4 Lines 44-48).
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche as applied to claim 10 above, and further in view of Leung et al (US 2022/0351972 A1, hereafter Leung).
Regarding claim 12, Bouche discloses the method of claim 10.
Bouche fails to disclose the first hardmask layer comprising a dielectric material selected from the group consisting of: silicon nitride (SiN), silicon oxynitride (SiON), silicon nitride-based material, and combinations thereof, and the second hardmask layer comprising a metal oxide material.
Leung discloses a first hardmask layer (Leung Fig. 3E 320) comprised of silicon nitride ([0036]) and a second hardmask layer (Leung Fig. 3E 325) comprised of a metal oxide ([0036]). Leung is analogous to Bouche and Kim in the field of etching and semiconductor processing.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the formation of hardmasks of Bouch using the listed materials specified by Leung to provide improved etch selectivity (Leung [0020]).
8. Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche as applied to claim 10 above, and further in view of Chen et al US (2022/0320309 A1, hereafter Chen).
Regarding claim 13, Bouche discloses the method of claim 10.
Bouche fails to disclose prior to performing the second etching process, further comprising repeating the step of removing a portion of the exposed sidewall of the first hardmask layer.
Chen discloses repeating the step of removing a portion of the exposed side wall ([0037]). Chen is analogous to Bouche in the field of etching and semiconductor processing.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to repeat the removal step of Bouche, as shown in Chen, before the second etching process. One would be motivated to repeat the step to achieve a desired thickness ([0037]).
Regarding claim 14, Bouche discloses the method of claim 10.
Bouche fails to disclose subsequently to performing the second etching process, further comprising repeating the step of removing a portion of the exposed sidewall of the first hardmask layer.
Chen discloses repeating the step of removing a portion of the exposed side wall ([0037]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to repeat the removal step of Bouche, as shown in Chen, after performing the second etching process. One would be motivated to repeat the step to achieve a desired thickness (Chen [0037]).
9. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Bouche and Chen as applied to claim 14 above, and further in view of Longo Pazos et al (US 2022/0392773 A1, hereafter Longo Pazos).
Regarding claim 15, Bouche and Chen disclose the method of claim 14.
Bouche and Chen fail to disclose subsequently to repeating the step of removing a portion of the exposed sidewall of the first hardmask layer, further comprising performing a third etching process on the metallic layer.
Longo Pazos discloses performing repeating an etching process on the metallic layer ([0023]). Longo Pazos is analogous to Bouche and Chen in the field of etching and semiconductor processing.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to repeat the step of etching the metallic layer in the method of Bouche and Chen, as shown in Longo Pazos, after removing the sidewall. One would be motivated to repeat the step to achieve finer control over the thickness of the metallic layer or the patterns being etched (Longo Pazos [0005]).
10. Claims 1, 9, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche in view of Kim et al (KR 101057191 B1, hereafter Kim).
Regarding claim 1, Bouche discloses a method for fabricating semiconductor devices, comprising:
sequentially forming at least a first hardmask layer (Bouche Fig. 1 14; Col. 2 Rows 21-23) and a second hardmask layer (Bouche Fig. 1 16; Col. 2 Rows 21-23) over a metallic layer (Bouche Fig. 1 12; Col. 2 Rows 21-23);
patterning the second hardmask layer (Bouche Fig. 5 16; Col. 3 Rows 42-43) and then the first hardmask layer (Bouche Fig. 5 14; Col. 4 Rows 10-11);
and etching the metallic layer (12; Col. 5 Rows 10-12) using a remaining portion of the first hardmask layer (14) as a mask.
Bouche fails to disclose oxidizing a sidewall of the patterned first hardmask layer and removing the oxidized sidewall of the first hardmask layer.
Kim discloses oxidizing a sidewall (Kim Fig. 5 135; [0028]) of the patterned first hardmask layer (Kim Fig. 5 130b; [0028]) and removing (Kim Fig. 6) the oxidized sidewall (135) of the first hardmask layer (130b). Kim is analogous to Bouche in the field of etching and semiconductor processing.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the etching process to recess the first hardmask layer of Bouche with the oxidation and removal process of Kim to provide finer control over the dimensions of the hardmask pattern, as evidenced by Chen (Chen [0037]).
Regarding claim 9, Bouche and Kim disclose the method of claim 1, wherein the remaining portion of the first hardmask layer (14) has a first dimension (annotated Bouche Fig. 7 L1) and the patterned second hardmask layer (16) has a second dimension (annotated Bouche Fig. 7 L2), and wherein the first dimension (L1) is smaller than the second dimension (L2) (Bouche Fig. 7; Col. 4 Lines 44-48).
Regarding claim 18, Bouche discloses a method for fabricating semiconductor devices, comprising:
forming a first hardmask layer (Fig. 1 14; Col. 2 Rows 21-23) over a metallic layer (Fig. 1 12; Col. 2 Rows 21-23); forming a second hardmask layer (Fig. 1 16; Col. 2 Rows 21-23) over the first hardmask layer (14);
performing a first etching process (Fig. 5; Col. 4 Rows 10-11) to pattern the first hardmask layer (14) through the second hardmask layer (16);
removing (Col. 4 Rows 41-42) the sidewall (annotated Fig 7 14S) of the first hardmask layer (14) through flowing an ion-free etchant gas (Col. 4 Rows 48-50);
and performing a second etching process (Col. 5 Rows 10-12) using a remaining portion of the first hardmask layer (14) as a mask to pattern the metallic layer (12).
Bouche fails to disclose oxidizing a sidewall of the patterned first hardmask layer and removing the oxidized sidewall of the first hardmask layer through flowing an ion-free etchant gas;
Kim discloses oxidizing a sidewall (Kim Fig. 5 135; [0028]) of the patterned first hardmask layer (Kim Fig. 5 130b; [0028]) and removing (Kim Fig. 6) the oxidized sidewall (135) of the first hardmask layer (130b).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the etching process to recess the first hardmask layer of Bouche with the oxidation process of Kim to provide finer control over the dimensions of the hardmask pattern, as evidenced by Chen (Chen [0037]). Furthermore, it would be obvious to substitute the ion-free etchant gas of Bouche to a different gas that is able to etch the oxidized sidewall, as evidenced by Chen (Chen [0033]).
Regarding claim 20, Bouche and Kim disclose the method of claim 18, wherein the remaining portion of the first hardmask layer (14) has a first dimension (annotated Bouche Fig. 7 L1) and the patterned second hardmask layer (16) has a second dimension (annotated Bouche Fig. 7 L2), and wherein the first dimension (L1) is smaller than the second dimension (L2) (Bouche Fig. 7; Col. 4 Lines 44-48).
11. Claims 4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche and Kim as applied to claims 1 and 18 above, and further in view of Leung.
Regarding claim 4, Bouche and Kim disclose the method of claim 1.
Bouche and Kim fail to disclose the first hardmask layer comprising a dielectric material selected from the group consisting of: silicon nitride (SiN), silicon oxynitride (SiON), silicon nitride-based material, and combinations thereof, and the second hardmask layer comprising a metal oxide material.
Leung discloses a first hardmask layer (Leung Fig. 3E 320) comprised of silicon nitride ([0036]) and a second hardmask layer (Leung Fig. 3E 325) comprised of a metal oxide ([0036]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the formation of hardmasks of Bouch using the listed materials specified by Leung to provide improved etch selectivity (Leung [0020]).
Regarding claim 19, Bouche and Kim disclose the method of claim 18.
Bouche and Kim fail to disclose the first hardmask layer comprising a dielectric material selected from the group consisting of: silicon nitride (SiN), silicon oxynitride (SiON), silicon nitride-based material, and combinations thereof, and the second hardmask layer comprising a metal oxide material.
Leung discloses a first hardmask layer (Leung Fig. 3E 320) comprised of silicon nitride ([0036]) and a second hardmask layer (Leung Fig. 3E 325) comprised of a metal oxide ([0036]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the formation of hardmasks of Bouch using the listed materials specified by Leung to provide improved etch selectivity (Leung [0020]).
11. Claims 4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ku as applied to claims 1 and 18 above, and further in view of Leung.
Regarding claims 4 and 19, Ku disclose the method of claim 1 and further discloses (in [0022]) the first hardmask layer 15 comprising a dielectric material selected from the group consisting of: silicon nitride (SiN), silicon oxynitride (SiON), silicon nitride-based material, and combinations thereof.
However, Ku fails to disclose the second hardmask layer comprising a metal oxide material.
Leung teaches a first hardmask layer (Leung Fig. 3E 320) in combination with a second hardmask layer (Leung Fig. 3E 325) comprised of a metal oxide ([0036]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the formation of hardmasks of Ku using a metal oxide for the second hardmask layer as taught by Leung to provide improved etch selectivity (Leung [0020]).
12. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Bouche and Kim as applied to claim 1 above, and further in view of Chen.
Regarding claim 5, Bouche and Kim disclose the method of claim 1,
Bouche and Kim fail to disclose prior to etching the metallic layer, further comprising repeating the step of oxidizing a sidewall of the patterned first hardmask layer and the step of removing the oxidized sidewall of the first hardmask layer.
Chen discloses repeating the step of oxidizing a sidewall ([0037]) and the step of removing the oxidized sidewall ([0037]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to repeat the oxidation and removal step of Bouche and Kim, as shown in Chen, before etching the metallic layer. One would be motivated to repeat the step to achieve a desired thickness (Chen [0037]).
Regarding claim 6, Bouche and Kim disclose the method of claim 1,
Bouche and Kim fail to disclose subsequently to etching the metallic layer, further comprising repeating the step of oxidizing a sidewall of the patterned first hardmask layer and the step of removing the oxidized sidewall of the first hardmask layer.
Chen discloses repeating the step of oxidizing a sidewall ([0037]) and the step of removing the oxidized sidewall ([0037]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to repeat the oxidation and removal step of Bouche and Kim, as shown in Chen, after the etching of the metallic layer. One would be motivated to repeat the step to achieve a desired thickness (Chen [0037]).
13. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Bouche, Kim, and Chen as applied to claim 6 above, and further in view of Longo Pazos.
Regarding claim 7, Bouche, Kim, and Chen disclose the method of claim 6.
Bouche, Kim, and Chen fail to disclose subsequently to repeating the step of oxidizing a sidewall of the patterned first hardmask layer and the step of removing the oxidized sidewall of the first hardmask layer, further comprising etching again the metallic layer.
Longo Pazos discloses performing repeating an etching process on the metallic layer ([0023]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to repeat the step of etching the metallic layer in the method of Bouche, Kim, and Chen, as shown in Longo Pazos, after the oxidation and removal of the sidewall. One would be motivated to repeat the step to achieve finer control over the thickness of the metallic layer or the patterns being etched (Longo Pazos [0005]).
Conclusion
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/MICHAEL B SUN/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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