DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 03/27/2024 and 12/27/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Clai ms 1-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (KR Pub No KR20040106657A ) in view of Ikeda (U.S. PG Pub No US2007 / 0139642A1 ) . *see attached translation for [] citations of Choi * Regarding claim 1, Choi teaches a method [see fig. 5, 0035] , comprising: I lluminating (via light source 36) fig. 5 [0037, 0040] an underside of a platen (12) fig. 5 [0028] positioned within a chamber (30/10) fig. 5 [0010, 0038] (all sides of platen 12 may be illuminated by 36 depending on rotational-position of 12 [0023, 0028, 0043] ; is shown with 360 - degree range of motion about vertical axis) ; detecting a perimeter edge ( detecting position of edge /shape of 38 in 12) fig. 5 [0038, 0043, 0048] of the platen (12 comprising 38 ) using an imaging device (34) fig. 5 [0036, 0048] positioned external to [0039] the chamber (30/10) ; determining, via a controller [0036] , position data [0036, 0041] for the platen (12) based on the detected perimeter edge (edge of 38 shape ) of the platen (12 with 38 ) ; positioning a wafer (W) fig. 5 [0037] atop the platen (12) based on the position data [0036-0037] of the platen (12) ; detecting a position [0041-0042] of the wafer (W) using the imaging device (34) [0043] ; and comparing the position data [0043] of the platen (12 comprising 38 and W) [0044] to the detected position of the wafer (W) (multiple images of wafer W position used to compare relative positions of wafer W [0043]) . However, Choi does not explicitly disclose wherein the wafer (W) comprises a positioning notch; and detecting a position of the wafer (W) and a position of the positioning notch using the imaging device (34) (positioning notch not shown). Ikeda teaches a method [see title] wherein the wafer (W) fig. 5 [0093] comprises a positioning notch (K) fig. 5 [0094]; and detecting (“determining”) a (center) position [0093] of the wafer (W) and a (peripheral) [0094-0096] position of the positioning notch (K) using the imaging device (36A) fig. 4 [0094] . Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have wafer placing method of Choi to include the notch in the periphery of the wafer [0092, 0094-0096] and complimentary detection method [0005, 0010, 0093] of Ikeda in order to improve the accuracy of detection [0010, 0021, 0124-0125] of both the periphery and center of the wafer [0124, 0128] to improve the efficiency and accuracy of wafer handling and placement [0010, 0021, 0125], as taught by Ikeda . Regarding claim 2, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 1. Choi also teaches further comprising determining whether to proceed to an implant process [0022, 0058] based on a comparison of the detected position [ 0031, 0034-0035 , 0052-0056 ] of the platen (12 , relative to W) fig. 5 [0028] to an expected reference position (‘stored image’ reference position compared with detected image position [0030-0031]) of the platen (12 , relative to W ) (once wafer W is placed successfully on platen 12 , method proceeds with end-step ion implantation on 12 [0058]). Regarding claim 3, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 1. Choi in view of Ikeda (with reference to Ikeda ) also teaches further comprising comparing the (“actual”, “identified” [0095]) position of the positioning notch (K) fig. 5 [0094-0095] to an expected (“calculated” [0094]) notch position (K) [0094] . Regarding claim 4, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 3. Choi in view of Ikeda (with reference to Ikeda ) also teaches further comprising rotating [0122] the platen ( 7 ) fig. 5 [0111-0112] to align the positioning notch (K) fig. 5 [0094] with the expected notch position (identified position of K is aligned with reference position by rotation [0122]) . Regarding claim 5, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 4. Choi also teaches wherein the platen (12) fig. 5 [0028] is rotated [0028] when (while) the platen (12) moves to (eventual) an implant position (final position at which implantation proceeds [0058] is achieved by rotation [0028] of platen 12 with chuck 38 during positioning steps [0028, 0053-0055] ) . Regarding claim 6, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 3. Choi also teaches further comprising determining whether to proceed to an implant process (after placement [0058]) based on the comparison [0043] of the detected position [0043, 0054] of the wafer (W) fig. 5 [0054] to the position data (stored image of 38) [0043] of the platen (12 with 38) fig. 5 [0043, 0053-0055]. Further, Choi in view of Ikeda (with reference to Ikeda ) teaches and based on the comparison of the (“actual”, “identified” [0095 Ikeda ]) position of the positioning notch (K) fig. 5 [0094-0095] to the expected (“calculated” [0094]) notch position (implantation process [0058 Choi ] would be further informed by notch positioning when notch (K) fig. 5 [0094 Ikeda ] of Ikeda incorporated to wafer of Choi ). Regarding claim 7, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 1. Choi also teaches further comprising positioning an illumination source (36) fig. 5 [0037] beneath the platen (12 with 38) fig. 5 [0038, 0037] ( see annotated fig. 5 for perspective in which 36 is beneath 12). wherein detecting the position of the wafer (W) fig. 5 [0043] comprises detecting a center point (shape including implied center point) of the platen (12 including 38) fig. 5 [0037, 0028] based on the detected perimeter edge (edge of illuminated shape of 38) [0037], and wherein positioning the wafer (W) atop the platen (12 with 38) further comprises aligning [0043, 0053-0056] a center point (shape including implied center point) of the wafer (W) with the center point (shape including implied center point) of the platen (12 with 38) (shapes, and implied centers, of wafer W and chuck 38 of 12 are determined and aligned [0043, 0053-0056]). Annotated fig. 5 of Choi designating perspective from which apparatus considered Regarding claim 8, Choi teaches a system [see fig. 5, 0035] for in-situ (on-site shown in fig. 5) verification (“detection” [0043]) and correction (“alignment” [0045]) of a wafer position (W) fig. 5 [0036] , the system [see fig. 5, 0035] comprising: an illumination device ( light source 36) fig. 5 [0037, 0040] to illuminate an underside of a platen (12) fig. 5 [0028] (all sides of platen 12 may be illuminated by 36 depending on rotational-position of 12 [0023, 0028, 0043]; is shown with 360-degree range of motion about vertical axis), wherein the platen (12) is positioned within a chamber (30/10) fig. 5 [0010, 0038] , wherein the illumination device (36) is positioned external [0039] to the chamber (30/10), and wherein the illumination device (36) is operable to (able to): detect a perimeter edge (detecting position of edge/shape of 38 in 12) fig. 5 [0038, 0043, 0048] of the platen (12 comprising 38) ; detecting a perimeter edge (shape) [0041, 0048, 0054] of a wafer (W) fig. 5 [0037] positioned atop the platen (38 with 12); a controller [0036] in communication with [0036-0037] the illumination device (36) and the platen (12 with 38) (through exchange and detection of light [0037]), wherein the controller [0036] is operable to (able to, through connection with camera unit 34 [0036-0037]): determine position data for the platen (12 with 38) based on the detected perimeter edge (edge of illuminated shape of 38) [0037] of the platen; determine a position [0043, 0045, 005 4 -0055] of the wafer (W); and compare the position (“alignment”) [0042, 0053, 0056] of the wafer (W) to the position data of the platen (38 with 12). However, Choi does not explicitly disclose a system to detect a perimeter edge of a wafer ( W ) positioned atop the platen (38 of 12) and a position of a positioning notch formed in the wafer; determine a position of the wafer (W) and a position of the positioning notch; and compare the position of the positioning notch to an expected notch position (notch not disclosed) . Ikeda teaches a system [see title , fig. 4, fig. 5 0088, 0093 ] to detect [0093-0096] a perimeter edge (outer peripheral end) [0093] of a wafer (W) fig. 5 [0093] positioned atop the platen (7) fig. 5 [0093] and a position of a positioning notch (K) fig. 5 [0094] formed in the wafer (W); determine (“identify” [0095]) a position of the wafer (W) and a position of the positioning notch (K); and compare the (“actual”, “identified” [0095]) position of the positioning notch (K) to an expected notch (K) (“calculated” [0094]) position [0093-0096]. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have wafer placing method of Choi to include the notch in the periphery of the wafer [0092, 0094-0096] and complimentary detection method [0005, 0010, 0093] of Ikeda in order to improve the accuracy of detection [0010, 0021, 0124-0125] of both the periphery and center of the wafer [0124, 0128] to improve the efficiency and accuracy of wafer handling and placement [0010, 0021, 0125], as taught by Ikeda . Regarding claim 9, Choi in view of Ikeda teaches the system [see fig. 5, 0035] of claim 8. Choi in view of Ikeda (with reference to Ikeda ) also teaches wherein the controller (41) fig. 4 [0095] is further operable to rotate [0122] the platen (7 ) fig. 5 [0111-0112] to align the positioning notch (K) fig. 5 [0094] with the expected notch position (identified position of K is aligned with reference position by rotation [0122]). Regarding claim 10, Choi in view of Ikeda teaches the system [see fig. 5, 0035] of claim 8. Choi also teaches wherein the controller [0036] is further operable to (able to) rotate [0028] the platen (12 with 38) fig. 5 [0028, 0037] when (while) the platen (12) moves to (eventual) an implant position (final position at which implantation proceeds [0058] is achieved by rotation [0028] of platen 12 with chuck 38 during positioning steps [0028, 0053-0055]). Regarding claim 11, Choi in view of Ikeda teaches the system [see fig. 5, 0035] of claim 8. Choi also teaches wherein the controller [0036] is further operable to (able to) determine whether to proceed to an implant process (after placement [0058]) based on the comparison [0043] of the detected position [0043, 0054] of the wafer (W) fig. 5 [0054] to the position data (stored image of 38) [0043] of the platen (12 with 38) fig. 5 [0043, 0053-0055]. Regarding claim 12, Choi in view of Ikeda teaches the system [see fig. 5, 0035] of claim 8. Choi also teaches wherein the controller [0036] is further operable to (able to) determine whether to proceed to an implant process [0022, 0058] based on a comparison of the detected position [0031, 0034-0035] of the platen (12, relative to W) fig. 5 [0028] to an expected reference position (‘stored image’ reference position compared with detected image position [0030-0031]) of the platen (12, relative to W) (once wafer W is placed successfully on platen 12, method proceeds with end-step ion implantation on 12 [0058]). Regarding claim 13, Choi in view of Ikeda teaches the system [see fig. 5, 0035] of claim 8. Choi also teaches wherein the controller [0036] is further operable to (able to) detect a center point (shape including implied center point) of the platen (12 including 38) fig. 5 [0037, 0028] based on the detected perimeter edge (edge of illuminated shape of 38) [0037] , and wherein the wafer (W) fig. 5 [0043] is positioned atop the platen (12 with 38) by aligning [0043, 0053-0056] a center point of the wafer (shape including implied center point) of the wafer (W) with the center point (shape including implied center point) of the platen (12 with 38) (shapes, and implied centers, of wafer W and chuck 38 of 12 are determined and aligned [0043, 0053-0056]). Regarding claim 14, Choi teaches a method [see fig. 5, 0035] for in-situ (on-site shown in fig. 5) verification (“detection” [0043]) and correction (“alignment” [0045]) of a wafer position (W) fig. 5 [0036], the method [see fig. 5, 0035] comprising: illuminating (via light source 36) fig. 5 [0037, 0040] an underside of a platen (12) fig. 5 [0028] positioned within a processing chamber (30/10) fig. 5 [0010, 0038] (all sides of platen 12 may be illuminated by 36 depending on rotational-position of 12 [0023, 0028, 0043]; is shown with 360-degree range of motion about vertical axis); detecting a perimeter edge (detecting position of edge/shape of 38 in 12) fig. 5 [0038, 0043, 0048] of the platen (12 comprising 38) using an imaging device (34) fig. 5 [0036, 0048] positioned external to [0039] the processing chamber (30/10), above the platen (in perspective as shown in fig. 5); determining, via a controller [0036], position data [0036, 0041] for the platen (12) based on the detected perimeter edge (edge of 38 shape ) of the platen (12 with 38 ); positioning a wafer (W) fig. 5 [0037] atop the platen (12) based on the position data [0036-0037] of the platen (12); detecting a position [0041-0042] of the wafer (W) using the imaging device (34) [0043]; and comparing the position data [0043] of the platen (12 comprising 38 and W) [0044] to the detected position of the wafer (W) (multiple images of wafer W position used to compare relative positions of wafer W [0043]). However, Choi does not explicitly disclose wherein the wafer (W) comprises a positioning notch; and detecting a position of the wafer (W) and a position of the positioning notch using the imaging device (34) (positioning notch not shown). Ikeda teaches a method [see title] wherein the wafer (W) fig. 5 [0093] comprises a positioning notch (K) fig. 5 [0094]; and detecting (“determining”) a (center) position [0093] of the wafer (W) and a (peripheral) [0094-0096] position of the positioning notch (K) using the imaging device (36A) fig. 4 [0094]. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have wafer placing method of Choi to include the notch in the periphery of the wafer [0092, 0094-0096] and complimentary detection method [0005, 0010, 0093] of Ikeda in order to improve the accuracy of detection [0010, 0021, 0124-0125] of both the periphery and center of the wafer [0124, 0128] to improve the efficiency and accuracy of wafer handling and placement [0010, 0021, 0125], as taught by Ikeda . Regarding claim 15, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 14. Choi in view of Ikeda (with reference to Ikeda ) also teaches further comprising comparing the (“actual”, “identified” [0095]) position of the positioning notch (K) fig. 5 [0094-0095] to an expected (“calculated” [0094]) notch position (K) [0094]. Regarding claim 16, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 15. Choi in view of Ikeda (with reference to Ikeda ) also teaches further comprising rotating [0122] the platen (7) fig. 5 [0111-0112] to align the positioning notch (K) fig. 5 [0094] with the expected notch position (identified position of K is aligned with reference position by rotation [0122]). Regarding claim 17, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 16. Choi also teaches wherein the platen (12) fig. 5 [0028] is rotated [0028] when (while) the platen (12) moves to (eventual) an implant position (final position at which implantation proceeds [0058] is achieved by rotation [0028] of platen 12 with chuck 38 during positioning steps [0028, 0053-0055]). Regarding claim 18, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 15. Choi also teaches further comprising determining whether to proceed to an implant process [0022, 0058] based on each of the following: a comparison of the detected position [0031, 0034-0035, 0043, 0055 Choi ] of the platen (12 with 38, relative to W) fig. 5 [0028] to an expected reference position (‘stored image’ reference position compared with detected image position [0030-0031]) of the platen (12, relative to W) (once wafer W is placed successfully on platen 12, method proceeds with end-step ion implantation on 12 [0058]), the comparison of the detected position (detected alignment) of the wafer (W) [0043, 0045, 0052-0055] to the position data of the platen (12 with 38) [0052-0056]. Further, Choi in view of Ikeda (with reference to Ikeda ) also teaches further comprising determining whether to proceed to an implant process (implantation process [0058 Choi ] would be further informed by notch positioning when notch (K) fig. 5 [0094 Ikeda ] of Ikeda incorporated to wafer of Choi ) based the comparison of the (“actual”, “identified” [0095 Ikeda ]) position of the positioning notch (K) fig. 5 [0094-0095] to the expected (“calculated” [0094]) notch position Regarding claim 20, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 14. Choi also teaches further comprising detecting a center point (shape including implied center point) of the platen (12 including 38) fig. 5 [0037, 0028] based on the detected perimeter edge (edge of illuminated shape of 38) [0037] , wherein positioning the wafer (W) atop the platen (12 with 38) further comprises aligning [0043, 0053-0056] a center point (shape including implied center point) of the wafer (W) with the center point (shape including implied center point) of the platen (12 with 38) (shapes, and implied centers, of wafer W and chuck 38 of 12 are determined and aligned [0043, 0053-0056]). Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (KR Pub No KR20040106657A ) modified by Ikeda (U.S. PG Pub No US2007 / 0139642A1 ), as applied in claim 14 above, and further in view of Shih (U.S. PG Pub No US2020 / 0072760A1 ). Regarding claim 19, Choi in view of Ikeda teaches the method [see fig. 5, 0035] of claim 14. However, Choi in view of Ikeda does not explicitly disclose further comprising positioning an illumination source beneath the platen (12 including 38) fig. 5 [0037, 0028] (in orientation shown in fig. 5) . Shih teaches a method [see fig. 4C, 0048] further comprising positioning an illumination source (21) fig. 4C [0040] beneath the platen (11 holding substrate 1) fig. 4C [0034, 0048] (in addition to light source 31 [0048] above 11). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Choi in view of Ikeda to include an additional illumination source [0034, 0040] beneath the platen [0048] in addition to the upper light source [0048] in order to improve the efficiency [0029-0030] and accuracy [0051] of inspection operations during substrate/wafer processing [0048], as taught by Shih . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shindo (U.S. PG Pub No US2021/00252695A1) and Koelmel (U.S. PG Pub No 2013 / 0287536 ) teach another example of wafer positioning involving notch-markings. Aikawa (U.S. PG Pub No US2014 /0 174351A1 ) teaches another example of a wafer positioning method involving a chamber, illumination source, and camera. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT SEAN AYERS WINTERS whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3308 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday 10:30 am - 7:00 pm (EST) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SEAN AYERS WINTERS/ Examiner, Art Unit 2892 03/10/2026 /NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892