Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Allowable Subject Matter
Claim 20, and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al. (US 2018/0308801 A1) in view of Lin et al. (US 20230402385 A1).
CLAIM 17. Shih et al. teaches method of forming a semiconductor device, comprising:
forming a multilayer, the multilayer comprising a plurality of aluminum nitride 24 layers interleaved by a plurality of aluminum oxide layers 26 or a plurality of aluminum nitride layers interleaved by a plurality of aluminum oxynitride layers;
forming a substrate 27 and a dielectric layer 42 over the multilayer; and
forming a conductive pattern 72 in the multilayer 24/26 , the substrate 27 and the dielectric laver 42 (¶19 & Fig. 1-8).
Shih is silent upon “a plurality of conductive patterns.” The prior art reference teaches a layer containing a single conductive structure. A PHOSITA seeking to optimize circuit layout, reduce parasitic capacitance, or provide multiple independent electrical pathways within the same layer would recognize that a single conductive structure can be divided, etched, or patterned into a plurality of distinct conductive patterns.
Splitting a single conductive element into multiple discrete traces or patterns is a routine design choice and a matter of predictable engineering design. See Lin et al. Fig. 1, which demonstrates a lower AlN layer over a IC substrate with a dielectric layer thereon, and multiple metallization patterns formed therein passing through both the dielectric and AlN layer. The modification requires nothing more than the application of conventional photolithography and etching techniques well known in the art.
Furthermore, doing so yields the entirely predictable result of providing multiple independent electrical signals within the same material layer. Therefore, the limitation of "forming a plurality of conductive patterns in the layer" represents a workshop modification of the cited reference that lacks patentable weight and would have been obvious to the PHOSITA.
Claim(s) 17-19, 21-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al. (US 2018/0308801 A1) in view of Lin et al. (US 20230402385 A1) in view of Shiba (US 20170062209 A1).
Claims 18 and 17. Shih et al. in view of Lin method of claim 17, wherein forming the multilayer comprises performing a plurality of process cycles, and each cycle comprises:
depositing an aluminum nitride layer; and
forming an aluminum oxide layer or an aluminum oxynitride layer at the surface of the AlN layer.
Shih does not explicitly disclose treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer to an aluminum oxide layer or an aluminum oxide nitride layer.
Shiba teaches methods of forming ultrathin dielectric barrier and etch-stop film stacks utilizing aluminum nitride (AlN) and aluminum oxide (AlO) layers (see Shiba, ¶35-40).
While Shiba teaches providing an aluminum oxide layer directly on an aluminum nitride layer, Shiba does not explicitly disclose forming the aluminum oxide layer by treating and converting a top portion of the underlying aluminum nitride layer.
However, it would have been obvious to a person of ordinary skill in the art (POSITA) at the time of the invention to modify the method of Shih, in view of Shiba's teaching of providing an AlO/AlN dielectric stack, by forming the upper aluminum oxide (or aluminum oxide nitride) portion by treating and converting the exposed top portion of the aluminum nitride layer rather than depositing a separate, discrete layer.
One of ordinary skill in the art would have been motivated to utilize a surface conversion treatment (e.g., exposing the exposed surface of the aluminum nitride layer to an oxidizing plasma or ambient) as an obvious process selection and design choice because chemical surface conversion and additive layer deposition are well-known alternative processing techniques for forming ultrathin dielectric capping regions. A POSITA would have selected surface conversion to simplify processing steps, eliminate additional precursor deposition cycles, and ensure a continuous, defect-free oxide/oxynitride passivation interface without undesirably increasing overall film stack thickness.
Additionally regarding claims 17 and 18, Lin et al. teaches method of forming a semiconductor device, comprising:
forming a layer, the layer comprising a aluminum nitride 24;
forming a substrate and a dielectric layer 106b (damascene implies at least two dielectric layers to form the shape of the conductive pattern, thus a substrate and a dielectric layer) over the layer 108; and
forming a conductive pattern M/V in the layer 108, the substrate 106b and the dielectric laver 106b (Lin Fig. 1).
Lin is silent upon the multilayer structure. The prior art reference teaches a layer containing a single conductive structure.
As demonstrated by and taught by Shiba, a AlN etch stop layer may be replaced by a multilayer of AlN/AlO [and/or AlNO] layer by sequentially depositing AlN and AlO by performing a plurality of processing cycles to form a functionally equivalent layer with improved performance (ie.. leakage, dielectric properties, etc.).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the AlN layer of Lin et al with with the AlN/AlO layer as taught by Shiba, since simple substitution of one known element for another to obtain predictable results of a improved etch stop layer is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 19. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 18, wherein treating the aluminum nitride layer comprises a nitrous oxide (N20) plasma treatment (Shiba ¶30).
CLAIM 21. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of forming a semiconductor device, comprising:
providing a first integrated circuit 22 comprising a first dielectric layer (Shih - ¶17);
forming a first multilayer 32 over the first dielectric layer of the first integrated circuit, wherein the first multilayer comprises a first layer and a second layer, the first layer is an aluminum nitride (AlN) layer 24, and the second
layer is one of an aluminum oxide (AlO) layer 26 and an aluminum oxynitride (AlON) layer;
disposing a second integrated circuit 42/72 (¶37- the device of Shih is an in process substrate to have further processing and IC devices formed thereon. See Lin et al. Fig. 1 demonstrating conventional multiplication of parts, stacking multiple wiring/metallization levels.) on the first multilayer; and
forming a plurality of first conductive vias 72 at least in the first dielectric layer and the first multilayer.
Shih is silent upon “a plurality of conductive patterns.” The prior art reference teaches a layer containing a single conductive structure. A PHOSITA seeking to optimize circuit layout, reduce parasitic capacitance, or provide multiple independent electrical pathways within the same layer would recognize that a single conductive structure can be divided, etched, or patterned into a plurality of distinct conductive patterns.
Splitting a single conductive element into multiple discrete traces or patterns is a routine design choice and a matter of predictable engineering design. See Lin et al. Fig. 1, which demonstrates a lower AlN layer over a IC substrate with a dielectric layer thereon, and multiple metallization patterns formed therein passing through both the dielectric and AlN layer. The modification requires nothing more than the application of conventional photolithography and etching techniques well known in the art.
Furthermore, doing so yields the entirely predictable result of providing multiple independent electrical signals within the same material layer. Therefore, the limitation of "forming a plurality of conductive patterns in the layer" represents a workshop modification of the cited reference that lacks patentable weight and would have been obvious to the PHOSITA.
Further note, in a alternative, the device as shown in Lin et al. Fig. 1 teaches the claimed device structure, however teaches a AlN layer as opposed to the claimed AlN/AlO multilayer. As demonstrated by and taught by Shiba, a AlN etch stop layer may be replaced by a multilay AlN/AlO layer by sequentially depoiting AlN and AlO to form a functionally equivalent layer with improved performance (ie.. leakage, dielectric properties, etc.).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the AlN layer of Lin et al with with the AlN/AlO layer as taught by Shiba, since simple substitution of one known element for another to obtain predictable results of a improved etch stop layer is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 22. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 21, wherein a thickness difference between the first layer and the second layer is between about 40 A and about 90 A (Shih ¶19 provides similar thickness ranges. Note the claim recites “about” with is relative and subjective not providing definite bounds.)
While Shih may not explicitly teach a relative thickness difference within the precise range of 40–90 Å, the thickness parameters recited in the method claim fail to provide a patentably distinct manipulation or a non-obvious optimization of the prior art. One of ordinary skill in the art of semiconductor fabrication would have found it obvious to determine workable or optimal values for this relative thickness through routine experimentation to achieve desired device performance. This is because the relative thickness is a result-effective variable, and there is no evidence in the record indicating that the claimed range is critical or produces unexpected results. It is well-established that discovering the optimum or workable ranges of a result-effective variable within prior art conditions through routine experimentation is not inventive. See MPEP § 2144.05 (citing In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977)).
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 23. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 21, wherein forming the first multilayer comprises alternately forming a plurality of first layers and a plurality of second layers (Shih Fig. 2 and ¶19).
CLAIM 24. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 21, wherein the first multilayer interfaces with the first dielectric layer of the first integrated circuit (Shih Fig. 2-8 and ¶19-25).
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CLAIM 25. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 21, wherein the first multilayer interfaces with a semiconductor substrate of the second integrated circuit (Shih Fig. 2-8 and ¶19-25).
26. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 21, wherein the second integrated circuit comprises a second multilayer-, the second multilayer comprises a first layer and a second layer, the first layer of the second multilayer is an aluminum nitride (AIN) layer, and the second layer of the second multilayer is one of an aluminum oxide (AlO) layer and an aluminum oxynitride (AlON) layer (Shih Fig. 2-8 and ¶19-25 & 37 – From the teaching of Shih, it is a obvious expectation and understanding to a PHOSITA that the process of forming the IMD layers for metallization levels may be repeated thereby forming more complex stack 3D-IC device.).
CLAIM 27. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of forming a semiconductor device, comprising:
forming a first multilayer , the first multilayer comprising a plurality of aluminum nitride layers 24 interleaved by a plurality of aluminum oxide layers 26 or a plurality of aluminum nitride layers interleaved by a plurality of aluminum oxynitride layers;
forming a dielectric layer 42 over the first multilayer;
forming a plurality of openings 72 in the first multilayer and the dielectric layer;
and forming a plurality of first conductive patterns 72 in the openings (Shih Fig. 2-8 and ¶19-37).
Shih is silent upon “a plurality of conductive patterns.” The prior art reference teaches a layer containing a single conductive structure. A PHOSITA seeking to optimize circuit layout, reduce parasitic capacitance, or provide multiple independent electrical pathways within the same layer would recognize that a single conductive structure can be divided, etched, or patterned into a plurality of distinct conductive patterns.
Splitting a single conductive element into multiple discrete traces or patterns is a routine design choice and a matter of predictable engineering design. See Lin et al. Fig. 1, which demonstrates a lower AlN layer over a IC substrate with a dielectric layer thereon, and multiple metallization patterns formed therein passing through both the dielectric and AlN layer. The modification requires nothing more than the application of conventional photolithography and etching techniques well known in the art.
Furthermore, doing so yields the entirely predictable result of providing multiple independent electrical signals within the same material layer. Therefore, the limitation of "forming a plurality of conductive patterns in the layer" represents a workshop modification of the cited reference that lacks patentable weight and would have been obvious to the PHOSITA.
Further note, in a alternative, the device as shown in Lin et al. Fig. 1 teaches the claimed device structure, however teaches a AlN layer as opposed to the claimed AlN/AlO multilayer. As demonstrated by and taught by Shiba, a AlN etch stop layer may be replaced by a multilay AlN/AlO layer by sequentially depoiting AlN and AlO to form a functionally equivalent layer with improved performance (ie.. leakage, dielectric properties, etc.).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the AlN layer of Lin et al with with the AlN/AlO layer as taught by Shiba, since simple substitution of one known element for another to obtain predictable results of a improved etch stop layer is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 28. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 27, wherein forming the openings in the first multilayer and the dielectric layer comprises forming the openings penetrating through the first multilayer and the dielectric layer (Shih Fig. 2-8 and ¶19-37).
CLAIM 29. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 27, wherein a material of the dielectric layer comprises boron carbo-nitride (BCN) based material (Shih Fig. 2-8 and ¶25).
CLAIM 30. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 27, wherein forming the first conductive patterns comprises forming seed layers, forming conductive pillars and forming capping layers extending over the seed layers and the conductive pillars respectively (Lin et al. Fig. 1 – As shown in Lin conductive structures as claimed routinely have seed layers and cap layers, thus would be a obvious modification to Shih, or in the alternative already be present in the structure of Lin et al. as modified by Shiba (See regarding claim 18, 21 & 27).
CLAIM 31. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 27, wherein the first multilayer is formed over a first substrate of a first integrated circuit bonded to a second integrated circuit through a first bonding layer comprising a plurality of aluminum nitride layers interleaved by a plurality of aluminum oxide layers or a plurality of aluminum nitride layers interleaved by a plurality of aluminum oxynitride layers (Shih Fig. 2-8 and ¶19-37 and/or Lin as modified by Shiba – Note: claim recites “bonded” which is a function not a specific type bonding process. There is a inherent “bond” between layers.).
CLAIM 32. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 31, further comprising forming a through via penetrating through the first multilayer, the first substrate, the first bonding layer and a portion of the second integrated circuit (Shih Fig. 2-8 and ¶19-37).
CLAIM 33. (Previously presented) The method of claim 31, wherein the second integrated circuit comprises a second multilayer comprising a plurality of aluminum nitride layers interleaved by a plurality of aluminum oxide layers or a plurality of aluminum nitride layers interleaved by a plurality of aluminum oxynitride layers, and a plurality second conductive patterns in the second multilayer (Shih Fig. 2-8 and ¶19-37 and/or Lin as modified by Shiba).
CLAIM 34. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 27, further comprising forming at least one thermal dissipation pattern and a plurality second conductive patterns in a dielectric structure over the first multilayer, wherein the at least one thermal dissipation pattern comprises a plurality of aluminum nitride layers interleaved by a plurality of aluminum oxide layers or a plurality of aluminum nitride layers interleaved by a plurality of aluminum oxynitride layers (Shih Fig. 2-8 and ¶19-37 and/or Lin as modified by Shiba – Note: High thermal conductivity is a known property of AlN & AlO, thus the resultant heat dissipation is a inherent feature of the layer.).
CLAIM 35. Shih in view of Lin in view of Shiba or in the alternative Lin et al in view of Siba teach the method of claim 27, wherein forming the first multilayer comprises performing a plurality of process cycles, and each cycle comprises: depositing an aluminum nitride layer; and treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer to an aluminum oxide layer or an aluminum oxynitride layer by using a nitrous oxide (N20) plasma treatment (Shiba– Teaches using nitrous oxide which will convert the top surface of AlN and deposit AlON. The process introduces an oxygen precursor/plasma such as nitrous oxide to deposit the AlO layer directly over the AlN layer. Shiba notes that this resulting sub-monolayer laminate of alternating AlN and AlO effectively functions as, or converts the film properties into, an Aluminum Oxynitride AlON thin-film structure to reduce leakage current).
Conclusion
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/1/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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