DETAILED ACTION
This application, 18/391,742, attorney docket GF2023097-US-NP, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to GlobalFoundries U.S. Inc., and has an effective filing date of 12/21/2023. Applicant's election without traverse of Group I, claims 1-18 in the reply filed on 5/3/2026 is acknowledged. Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-18 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 recites, “wherein the first metal level in the first interconnect layer is the same as the second metal level in the second interconnect layer.” It is not clear what is the same, they are not the same layer as claimed or shown.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (U.S. 2023/0420492) in view of Chen (U.S. 2022/0045162).
As for claim 1,
Liang teaches in figure 1, semiconductor device comprising:
a dielectric layer 122 over a semiconductor substrate 102;
a first conductive layer 136 in the dielectric layer; a capacitor dielectric layer 134 in the dielectric layer; and
a second conductive layer 132 in the dielectric layer,
Liang does not teach that the second conductive layer encircles the capacitor dielectric layer and the first conductive layer. (Liang is silent on the top view of the electrodes, so does not teach an “encircling” electrode, which examiner interprets to be “surrounded on all sides”
However, Chen teaches forming the outer electrode 112, in a circular hole, so that it would encircle the dielectric 128 and inner electrode 116.
It would have been obvious to one skilled in the art at the effective filing date of this application to form the capacitors in a hole because it allows a single pattern followed by depositions to form the capacitor is a single-pattern fashion. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 2,
Liang in view of Chen makes obvious the semiconductor device of claim 1, and in the combination, Liang teaches that the second conductive layer has a width that is wider than a width of the first conductive layer. (In the upper portion, the width of the upper conductor 132 is wider)
As for claim 3,
Liang in view of Chen makes obvious the semiconductor device of claim 1, and in the combination, Liang teaches a first via contact (unlabeled, but shown connecting the 116 and 136) above and connected to the first conductive layer.
As for claim 4,
Liang in view of Chen makes obvious the semiconductor device of claim 3, and in the combination, Liang teaches a second via contact (106) above and connected to the second conductive layer, wherein the second via contact laterally overlaps with the first conductive layer. (both extend through 122, so overlap laterally across the page)
As for claim 5,
Liang in view of Chen makes obvious the semiconductor device of claim 3, wherein the first via contact is electrically isolated from the second conductive layer. (inherent in figure 1 to prevent the capacitor electrodes from shorting rendering the device unusable for its purpose).
As for claim 6,
Liang in view of Chen makes obvious the semiconductor device of claim 1, and in the combination, Liang teaches an insulating layer (104) above the semiconductor substrate.
As for claim 7,
Liang in view of Chen makes obvious the semiconductor device of claim 1, and Liang teaches an active layer (124) above the first conductive layer. ([0020]).
As for claim 8,
Liang in view of Chen makes obvious the semiconductor device of claim 7, and in the combination, Liang teaches another active layer (102) below the first conductive layer. ([0020]).
As for claim 9,
Liang in view of Chen makes obvious the semiconductor device of claim 1, and in the combination, Liang teaches the second conductive layer has an upper portion at a first metal (M1/103) level in the semiconductor device.
As for claim 10,
Liang in view of Chen makes obvious the semiconductor device of claim 1, wherein the second conductive layer has a lower portion at or above a first metal (M1 is 103) level in the semiconductor device.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Chen in further view of Liu et al. (U.S. 2023/0067299).
As for claims 11 and 12,
Liang in view of Chen makes obvious the semiconductor device of claim 1, but does not teach that the first conductive layer has sidewalls having a stepped profile.
However, Liu teaches in figure 2H, first conductive layer (42) and a second conductive layer (46) with a stepped profile.
It would have been obvious to one skilled in the art at the effective filing date of this application to substitute the capacitor shape of Liu in the device of Liang to increase the capacitance of the cells. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Yamashita (U.S. 2016/0020235).
As for claim 13,
Liang teaches in figure 1, semiconductor device comprising:
a first semiconductor substrate (102) having a first active layer;
a first dielectric layer (103) over the first semiconductor substrate;
a first conductive layer (112) and a second conductive layer (116) in the first dielectric layer, the second conductive layer is above the first conductive layer;
a first insulator layer (104) over the first conductive layer, wherein the first insulator layer spaces the first conductive layer from the second conductive layer;
a third conductive layer (136) and a fourth conductive layer (132) in a second dielectric layer, the third conductive layer directly contacting the second conductive layer (via stub 106) and the fourth conductive layer is above the third conductive layer, wherein the third conductive layer has sidewalls adjoining a top surface (sides and a top in an inverted U shape);
a second insulator layer over 134) and conformal to the sidewalls and the top surface of the third conductive layer, wherein the second insulator layer spaces the third conductive layer from the fourth conductive layer; and
a second semiconductor substrate (124) over the fourth conductive layer, the second semiconductor substrate having a second active layer.
Liang does not teach a second semiconductor substrate over the fourth conductive layer, the second semiconductor substrate having a second active layer.
However, Yamashita teaches in figure 4G a second semiconductor substrate 202 over the fourth conductive layer (402 is the bridging capacitor), the second semiconductor substrate having a second active layer. (Yamashita [0031]).
It would have been obvious to one skilled in the art at the effective filing date of this application to use a second level of semiconductor material to provide a denser device. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 14,
Liang in view of Yamashita makes obvious the semiconductor device of claim 13, and in the combination, Liang teaches the fourth conductive layer has an upper portion between lower portions, wherein the upper portion is substantially horizontal and has a topmost surface (sides and a top in an inverted U shape).
As for claim 15,
Liang in view of Yamashita makes obvious the semiconductor device of claim 14, and in the combination, Liang teaches that the first conductive layer has a lower portion arranged within a first metal level in a first interconnect layer, and the upper portion of the fourth conductive layer is arranged within a second metal level in a second interconnect layer,
wherein the first metal level in the first interconnect layer is the same as the second metal level in the second interconnect layer. (They are mirror images.)
As for claim 16,
Liang in view of Yamashita makes obvious the semiconductor device of claim 13, and in the combination, Liang teaches that the fourth conductive layer is connected to the first conductive layer (at 106).
As for claim 17,
Liang in view of Yamashita makes obvious the semiconductor device of claim 13, and in the combination, Liang teaches that the first insulator layer is connected to the second insulator layer (connected by layer 104).
As for claim 18,
Liang in view of Yamashita makes obvious the semiconductor device of claim 13, and in the combination, Liang teaches the first conductive layer has a top surface that is coplanar with a top surface of the second conductive layer (both are coplanar with the bottom of insulation 104).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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