Attorney’s Docket Number: 44023187US01
Filing Date: 12/21/2023
Claimed Foreign Priority Date: none
Applicant: Chen
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 04/20/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Independent claims 10 and 16 are allowable. The restriction requirement between Species 1 and 2, as set forth in the Office action mailed on 01/20/2026, has been reconsidered in view of the allowability of claims to the elected invention pursuant to MPEP § 821.04(a). The restriction requirement is hereby withdrawn as to any claim that requires all the limitations of an allowable claim. Specifically, the restriction requirement of 01/20/2026 is withdrawn. Accordingly, pending in the application are claims 1-20.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 1 recites the limitation “bonding the interconnect substrate to the multichip module,” at L. 10. There is insufficient antecedent basis for this limitation in the claim, and it is unclear how this feature relates to features previously recited in the claim.
Insofar as the original disclosure discusses the features “multichip module” and “packaged multichip module”: at Par. [0036]: interconnect substrate 218 is bonded to the multichip module 200 (i.e., the molded set of chips); then at Par. [0053]: stacked chips are attached to the multichip module 200, forming a packaged multichip module 300. As such, the examiner suggests the following amendment at L. 2 --molding a set of chips in a medium to form a multichip module--, which would set proper anteceding basis for the later recited “multichip module”.
Claims 2-9 depend from claim 1, thus inherit the deficiencies identified supra.
Allowable Subject Matter
Claims 10-20 are allowable.
Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action.
Claims 2-9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, the prior art fails to disclose or suggest a method for forming a packaged multichip module comprising: patterning a first plurality of patterned vias through the first interconnect layer and the interconnect substrate so that each have an opening that is configured to connect with an interconnect formed on each chip of a set of chips of the multichip module based at least in part on position and orientation information detected during a mapping of alignment marks formed on each chip in the set of chips; and bonding the interconnect substrate to the multichip module, wherein bonding comprises positioning and aligning the interconnect substrate to a molded set of chips such that the interconnects of each chip within the set of chips are aligned with the first plurality of patterned vias formed in the interconnect substrate.
Regarding claim 16, the prior art fails to disclose or suggest a packaged multichip module, comprising: a first interconnect layer disposed over a base substrate comprising a first plurality of patterned vias that are patterned based at least in part on position and orientation information detected during a mapping of the alignment marks and the plurality of interconnects; a second interconnect layer disposed over the first interconnect layer comprising a first contacting surface formed on one side of the second interconnect layer comprising a first plurality of metal interconnects that match a pattern of the first plurality of patterned vias and a second contacting surface formed on a second side of the second interconnect layer comprising a second plurality of metal interconnects that are configured to connect with an interconnect formed on a stacked chip; and a stacked chip attached to one or more of the chips of the multichip module via the interconnect substrate.
Conclusion
The reference made of record and not relied upon is considered pertinent to applicant's disclosure. The reference cited disclose a method for bonding an interconnect layer to a multichip module based on the mapping of chip alignment marks, and having some features/method steps similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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