Prosecution Insights
Last updated: May 29, 2026
Application No. 18/392,317

CURRENT-BASED BUILT-IN SELF-TEST FOR CIRCUIT COMPONENTS ARRANGED IN VARIED CONFIGURATIONS

Non-Final OA §112
Filed
Dec 21, 2023
Examiner
ISLA, RICHARD
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries LLC
OA Round
2 (Non-Final)
77%
Grant Probability
Favorable
2-3
OA Rounds
2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
315 granted / 411 resolved
+8.6% vs TC avg
Strong +15% interview lift
Without
With
+15.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
24 currently pending
Career history
441
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
76.8%
+36.8% vs TC avg
§102
8.9%
-31.1% vs TC avg
§112
11.2%
-28.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 411 resolved cases

Office Action

§112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 4/15/2026 has been entered. Comments The present communication is responsive to the filing of the Information Disclosure Statement on 4/15/2026. In reviewing the submitted documents and updating the search, the examiner noted a deficiency in the preamble of claim 19 that should be addressed in the next response (see claim rejection under 35 USC 112(b) below). Also, the examiner notes that the last communication (Notice of Allowance mailed 2/20/2026) includes an examiner’s amendment. The examiner suggests the applicant include a copy of the claims including the amendments in the next response or confirm in the response if the amendments should be entered through examiner’s amendments in the next communication. This Office Action is made Non-Final. Information Disclosure Statement The information disclosure statement (IDS) submitted on 4/15/2026 was filed after the mailing date of the Notice of Allowance on 2/20/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are presented in the preamble of the claim. Although the claim properly introduces a non-transitory computer-readable medium storing instructions, it doesn’t explicitly tie those instructions as being executed by the test controller. There’s a lack of clear distinction about the role of the instructions and what unit executes them so that the process may be performed. The examiner suggests amending the claim preamble in the following manner: “- 19. A non-transitory computer-readable medium storing instructions that, when executed by a test controller, cause the test controller associated with a self-testing circuit to preform a process comprising:” Claim 20 is also rejected as it inherits the deficiencies in claim 19 noted above. Allowable Subject Matter Claims 1-20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 1, the prior art of record doesn’t teach alone or in combination a method including the steps of measuring a first current drawn by a test block of a plurality of test blocks in a self-testing circuit when the set of components is in the first configuration, measuring a second current drawn by the test block when the set of components is in the second configuration, and determining a ratio of, or a difference between, the first current measured when the set of components is in the first configuration and the second current measured when the set of components is in the second configuration; and detecting a defect in the test block based on the ratio or the difference, in combination with all other elements recited in the claim. As to claims 2-14, the claims are allowed as they include the allowable subject matter in claim 1 above. Regarding claim 15, the prior art of record doesn’t teach alone or in combination a self-testing circuit comprising a current measurement circuit configured to measure a first current drawn by the test block and to measure a second current drawn by the test block, and a test controller configured to determine a ratio, or a difference between, the first current measured when the set of components is in the first configuration and the second current measured when the set of components is in the second configuration and detect a defect in the test block based on the ration or the difference, in combination with all other elements recited in the claim. As to claims 16-18, the claims are allowed as they include the allowable subject matter in claim 15 above. Claims 19-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Regarding claim 19, the prior art of record doesn’t teach alone or in combination, a non-transitory computer-readable medium storing instructions that, when executed by the test controller, cause the test controller to perform a process comprising: transmitting, to a test block of a plurality of test blocks in the self-testing circuit, a first test vector corresponding to a first configuration for a set of components in the test block; transmitting, to the test block, a second test vector corresponding to a second configuration for the set of components, the second configuration being different from the first configuration; determining a ratio of, or a difference between, a first current measured as the first current is drawn by the test block when the set of components is in the first configuration and a second current measured as the second current is drawn by the test block when the set of components is in the second configuration; and detecting a defect in the test block based on the ratio or the difference, in combination with all other elements recited. As to claim 20, the claims are allowed as they include the allowable subject matter in claim 19 above. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The Publications submitted with the IDS are directed to methods for monitoring current in semiconductor devices for the purpose of testing and/or identifying probability of faulty units within a semiconductor device. Neither the publications nor the prior art of record teaches alone or in combination the transmitting of vectors corresponding to a first and second configurations of components in the test block of a self-testing circuit. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Richard Isla whose telephone number is (571)272-5056. The examiner can normally be reached Monday-Friday 9a - 5:30p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD ISLA/Primary Patent Examiner, Art Unit 2858 May 2, 2026
Read full office action

Prosecution Timeline

Show 1 earlier event
Aug 27, 2025
Non-Final Rejection mailed — §112
Nov 05, 2025
Applicant Interview (Telephonic)
Nov 05, 2025
Examiner Interview Summary
Nov 21, 2025
Response Filed
Jan 21, 2026
Examiner Interview (Telephonic)
Apr 15, 2026
Request for Continued Examination
Apr 24, 2026
Response after Non-Final Action
May 06, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
77%
Grant Probability
92%
With Interview (+15.4%)
2y 8m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 411 resolved cases by this examiner. Grant probability derived from career allowance rate.

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