DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 8/5/2026. Claims 1, 2 & 4-21 are pending in this application. Claim 3 is canceled. Claim 20 is withdrawn. Claim 21 is new.
Claims 1, 4-19 & 21 are being examined in this Office Action.
Claim Objections
2. The claims are objected because of the following reasons:
Re claim 5: delete “claim 3”, and insert --claim 4-- because of “the insulator layer” claimed in claim 4.
Re claim 10, line 2: delete “though” and insert --through--.
Re claim 18, line 2: in front of “passivation layer” and insert --the--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1, 8, 10, 13, 15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dutta et al. (US 2022/0352359, “Dutta59”).
Re claim 1, Dutta59 teaches, under BRI, Figs. 4C-D, [0037, 0040, 0052-0054], a structure comprising:
-a first chiplet (HBT wafer 403) comprising a first device (HBT) with a backside metal (108) and a backside contact (vias & 113) (Fig. 4C); and
-a second chiplet (CMOS wafer 408) connected to the first chiplet (403), the second chiplet (408) comprising a second device (410, 412, 420, 422) with a frontside contact (in interposer 404) (Fig. 4D),
wherein the first device (HBT) comprises a heterojunction bipolar transistor comprising a sub-collector (112), a collector (114), a base (116) and an emitter (118), and the backside contact comprises a bottom contact (113) extending through a passivation layer (110) to directly contact the sub-collector (112), and the front contact (in 404) electrically connects the second device (in 408) to the heterojunction bipolar transistor (HBT).
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Re claim 8, Dutta59 teaches, Fig. 4C, wherein the backside contact (113, vias, 108) directly contacts the sub-collector (112) without contacting the collector (114).
Re claim 10, Dutta59 teaches, Figs. 4C-D, wherein the first device (HBT) is electrically connected to the second device (in 408) through wiring structures (in 404) between the first chiplet (403) and the second chiplet (408)
Re claim 13, Dutta59 teaches, under BRI, Figs. 4C-D, [0037, 0040, 0052-0054], a structure comprising:
-a first chiplet (HBT wafer 403) comprising a heterojunction bipolar transistor (HBT), the heterojunction bipolar transistor (HBT) comprising a sub-collector (112), a collector (114), a base (116) and an emitter (1118) (Fig. 4C);
-a backside contact (113, vias, 108) comprising a bottom contact (113) extending through a passivation layer (110) to directly contact the sub-collector (112) (Fig. 4C); and
-a second chiplet (CMOS wafer 408) connected to the first chiplet (403), the second chiplet (408) comprising a CMOS device (412, 422) with a frontside contact (in interposer 404) connecting to the heterojunction bipolar transistor (HBT) (Fig. 4D), the backside contact (113, vias, 108) being disposed on an opposite side of the heterojunction bipolar transistor (HBT) from the frontside contact (in interposer 404) (Fig.4C).
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Re claim 15, Dutta59 teaches, Fig. 5C, wherein a width of the base (116) is greater than a width of the emitter (118), a width of the collector (114) and a width of the sub-collector (112).
Re claim 18, Dutta59 teaches, Fig. 4C, wherein the backside contact (103, vias) extends through an insulator material (102) and passivation layer (110) on a backside of the first chiplet (403).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 2, 4, 8-10, 12-15, 18 and 19 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (US 2021/0098600) in view of Dutta et al. (US 2022/0352359, “Dutta59”).
Re claim 1, Dutta teaches, under BRI, Figs. 1 & 3, [0018, 0025, 0026, 0032], a structure comprising:
-a first chiplet (152, 340) comprising a first device (HBT 100) with a backside metal (190 or metal on 340) and a backside contact (vias 182, 184 & 120) (Figs. 1 & 3); and
-a second chiplet (306, 350) connected to the first chiplet (152, 340), the second chiplet (306, 350) comprising a second device (CMOS components 302, 304) with a frontside contact (contacts above 302, 304) (Fig. 3),
wherein the first device (100, Fig. 1) comprises a heterojunction bipolar transistor comprising a sub-collector (112), a collector (106), a base (104) and an emitter (102), and the backside contact comprises a bottom contact (120) to directly contact the sub-collector (112), and the front contact (contacts above 302, 304) electrically connects the second device (306, 350) to the heterojunction bipolar transistor (100).
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Dutta does not explicitly teach the bottom contact extending through a passivation layer.
Dutta59 teaches, Fig. 1, [0037, 0039], the bottom contact (113) extending through a passivation layer (110).
As taught by Dutta59, one of ordinary skill in the art would utilize & modify the above teaching to obtain the bottom contact extending through a passivation layer as claimed, because it aids in enhancing protection and electrical isolation in the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dutta59 in combination with Duttta due to above reason.
Re claim 2, Dutta teaches, Fig. 3, [0026, 0032], wherein the first device comprises a heterojunction bipolar transistor (HBT 100) and the second device comprises a CMOS transistor (CMOS components 302, 304) electrically connecting (e.g., vias 320, 322, 324 for electrical connection) to the heterojunction bipolar transistor (100).
Re claim 4, in combination cited above, Dutta59 teaches, under BRI, Fig. 1, [0037, 0040], wherein a width of the base (116) is greater than a width of the emitter (118), a width of the collector (114) and a width of the sub-collector (112), and the bottom contact (consider 113, 109) extends through an insulator layer (consider 110) beneath the passivation layer (consider 102).
Re claim 8, in combination cited above, Dutta59 teaches, Fig. 1, wherein the backside contact (consider 113, 109) directly contacts the sub-collector (112) without contacting the collector (114).
Re claim 9, in combination cited above, Dutta59 teaches, Fig. 1, [0038, 0039], wherein the backside contact (consider 113, 109) between the sub-collector (112) of the first device and a redistribution layer (consider 108), and the sub-collector (11) comprises doped semiconductor material (n+ InGaAs) and the backside contact (113, 109) electrically contacts the doped semiconductor material through the bottom contact (113).
Re claim 10, Dutta teaches, Fig. 3, wherein the first device (152, 340) is electrically connected to the second device (306, 350) though wiring structure (vias and structures over 302, 304) between the first chiplet (152, 340) and the second chiplet (306, 350).
Re claim 12, Dutta teaches, Fig. 1, [0018], wherein the collector (106) comprises a blanket implantation (112) in a bulk semiconductor substrate.
Re claim 13, Dutta teaches, under BRI, Figs. 1 & 3, [0025, 0026, 0032], a structure comprising:
-a first chiplet (152, 340) comprising a heterojunction bipolar transistor (HBT 100), the heterojunction bipolar transistor (HBT 100) comprising a sub-collector (112), a collector (106), a base (104) and an emitter (102) (Figs. 1 & 3);
-a backside contact (consider 120, 182, 184, 190) comprising a bottom contact (120) to directly contact the sub-collector (112); and
-a second chiplet (306, 350) connected to the first chiplet (152, 340), the second chiplet (306, 350) comprising a CMOS device (302, 304) with a frontside contact (e.g. contact above 302, 304) connecting to the heterojunction bipolar transistor (HBT 100), the backside contact (120, 182, 184, 190) (Fig. 1) being disposed on an opposite side of the heterojunction bipolar transistor (100) from the frontside contact (Fig. 3).
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Dutta does not explicitly teach the bottom contact extending through a passivation layer.
Dutta59 teaches, Fig. 1, [0037, 0039], the bottom contact (113) extending through a passivation layer (110).
As taught by Dutta59, one of ordinary skill in the art would utilize & modify the above teaching to obtain the bottom contact extending through a passivation layer as claimed, because it aids in enhancing protection and electrical isolation in the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dutta59 in combination with Duttta due to above reason.
Re claim 14, in combination cited above, Dutta teaches, Fig. 3, wherein the CMOS device comprises a transistor (302, 304) electrically connecting to the heterojunction bipolar transistor (100), and Dutta59 teaches, Fig. 1, the backside contact (consider 109) extends through an insulator layer comprising buried oxide (e.g., ILD 102).
Re claim 15, in combination cited above, Dutta59 teaches, Fig. 1, [0040], wherein a width of the base (116) is greater than a width of the emitter (118), a width of the collector (114) and a width of the sub-collector (112).
Re claim 18, in combination cited above, Dutta59 teaches, Fig. 1, wherein the backside contact (consider 109, 113) extends through an insulator material (102) and passivation layer (110) on a backside of the first chiplet (10).
Re claim 19, Dutta teaches, Fig. 1, wherein the backside contact (consider 120, 180, 182, 184, 186) connects between a sub-collector (112) of the first device to a redistribution layer (consider 188, 190, 192).
5. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dutta as modified by Dutta59 as applied to claims 1 & 10 above, and further in view of Zhu et al. (US 2019/0067105).
The teachings of Dutta/Dutta59 have been discussed above.
Re claim 11, Dutta/Dutta59 does not explicitly teach the wiring structures comprise 3D heterogeneously integrated (3DHI) contact structures.
Zhu teaches the use of 3D integrated wiring structure (abstract).
As taught by Zhu, one of ordinary skill in the art would utilize & modify the above teaching to obtain 3D heterogeneously integrated (3DHI) contact structures as claimed, because it aids in achieving a desired wiring structure that enables wiring through thick device layer at reduced cost.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Zhu in combination Dutta/Dutta59 due to above reason.
6. Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta as modified by Dutta59 as applied to claim 13 above, and further in view of Dutta (US 2020/0266290, “Dutta90”).
The teachings of Dutta/Dutta59 have been discussed above.
Re claim 16, Dutta/Dutta59 does not teach a third device connecting to the first device, the third device and the first device comprising a cascode power amplifier with the third device comprising a emitter contact through a backside.
Dutta90 teaches, Fig. 1, [0018], a third device (108) connecting to the first device (106), the third device (108) and the first device (106) comprising a cascode power amplifier (e.g., formed of two HBT devices) with the third device (108) comprising a emitter (122, 124) contact through a backside (e.g., via metal 1 & vias).
As taught by Dutta90, one of ordinary skill in the art would utilize & modify the above teaching to obtain a third device as claimed, because it aids in achieving desired device/structure with reduced module size and parasitic.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dutta90 in combination with Duttta/Dutta59 due to above reason.
Re claim 17, in combination cited above, Dutta90 teaches, Fig. 5, trench isolation structures (520) isolating the first device (502) from the third device (consider 504).
7. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Dutta as modified by Dutta59 as applied to claim 1 above, and further in view of Peng et al. (US 2022/0302255).
The teachings of Dutta/Dutta59 have been discussed above.
Re claim 21, Dutta/Dutta59 does not explicitly teach wherein the backside contact comprises tungsten.
Peng teaches the backside contact comprises tungsten [0042].
As taught by Peng, one of ordinary skill in the art would utilize & modify the above teaching to obtain tungsten as the contact, because tungsten in known and widely un the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Peng in combination with Duttta/Dutta59 due to above reason.
Allowable Subject Matter
8. Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
9. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen (US 2005/0035370, Fig. 4A) discloses a HBT having emitter mesa and sub-collector on a substrate.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/3/26
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