DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Group I, claims 1-19 in the reply filed on 4/8/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1, 2, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dutta et al. (US 2021/0098600).
Re claim 1, Dutta teaches, under BRI, [0025, 0026, 0032], a structure comprising:
-a first chiplet (152, 340) comprising a first device (HBT 100) with a backside contact (Metal 1 and/or with 120 & vias); and
-a second chiplet (306, 350) connected to the first chiplet (152, 340), the second chiplet (306, 350) comprising a second device (CMOS components 302, 304) with a frontside contact (contacts above 302, 304).
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Re claim 2, Dutta teaches, Fig. 3, [0026, 0032], wherein the first device comprises a heterojunction bipolar transistor (HBT 100) and the second device comprises a CMOS transistor (CMOS components 302, 304) electrically connecting (e.g., vias 320, 322, 324 for electrical connection) to the heterojunction bipolar transistor (100).
Re claim 8, Dutta teaches, under BRI, Fig. 3, [0026, 0030], wherein the backside contact (Metal 1 with vias 320, 322) extends through an insulator material (152) and passivation layer (340).
Re claim 10, Dutta teaches, Fig. 3, wherein the first device (100) connects to the second device (302, 304) by wiring structures (vias and structures over 302, 304) through interlayer dielectric material (350, 152) through the frontside contact.
3. Claims 1-3, 13 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 10,431,581).
Re claim 1, Li teaches, under BRI, cols. 3-4, a structure comprising:
-a first chiplet (indicated) comprising a first device (HBT 104) with a backside contact (108, 110 or 146, 148, 150); and
-a second chiplet (indicated) connected to the first chiplet (indicated), the second chiplet (indicated) comprising a second device (CMOS components 138, 140) with a frontside contact (142, 144).
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Re claim 2, Le teaches, Fig. 1, wherein the first device comprises a heterojunction bipolar transistor (HBT 104) and the second device comprises a CMOS transistor (CMOS device 102) electrically connecting (e.g., within an integrated structure) to the heterojunction bipolar transistor (HBT 104).
Re claim 3, Li teaches, under BRI, Fig. 1, wherein the first device (HBT 104) comprises a heterojunction bipolar transistor comprising a sub-collector (part of 112), a collector (114), a base (116) and an emitter (118), and the backside contact (108, 110 or 146, 148, 150) contacts to the sub-collector (part of 112) (e.g., electrical or via interlayers).
Re claim 13, Li teaches, under BRI, Fig. 1, cols. 3-4, a structure comprising:
-a first chiplet (indicated) comprising a heterojunction bipolar transistor (HBT 104), the heterojunction bipolar transistor (HBT 104) comprising a sub-collector (e.g., part of 112 contacting 114), a collector (114), a base (116) and an emitter (118);
-a backside contact (108, 110 or 146, 148, 150) contacting (electrical or via interlayers) to the sub-collector (part of 112); and
-a second chiplet (indicated) connected to the first chiplet (indicated), the second chiplet (indicated) comprising a CMOS device (102) with a frontside contact (142, 144) connecting to the heterojunction bipolar transistor (HBT 104).
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Re claim 14, Li teaches, Fig. 1, wherein the CMOS device (102) comprises a transistor electrically connecting (e.g. within integrated structure) to the heterojunction bipolar transistor (HBT 104).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 3, 9, 12-14, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta.
The teachings of Dutta have been discussed above.
Re claim 3, Dutta’s Fig. 3 teaches wherein the first device (HBT 100) [0025] comprises a heterojunction bipolar transistor comprising a collector, a base and an emitter, and the backside contact (Metal 1) contacts to the collector (through vias).
Dutta’s Fig. 3 does not explicitly teach a sub-collector and the backside contact contacts to the sub-collector.
Dutta’s Fig. 1 teaches, [0017, 0018], a sub-collector (112) and the backside contact (e.g., 120, 182, 184) contacts to the sub-collector (112).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Dutta’s Fig. 1 to obtain a sub-collector and the backside contact contacts to the sub-collector as claimed, because it aids in allowing for a reduction of base-collector-capacitance (Cbc) of the HBT & improving device power gain.
Re claim 9, in combination cited above, Dutta’s Fig. 1 teaches wherein the backside contact (180, 182, 184, 186) connects between a sub-collector (112) of the first device to a redistribution layer (188, 190, 192).
Re claim 12, in combination cited above, Dutta’s Fig. 1 teaches, [0018], wherein the collector (106) comprises a blanket implantation (112) in a bulk semiconductor substrate.
Re claim 13, Dutta teaches, under BRI, [0025, 0026, 0032], a structure comprising:
-a first chiplet (152, 340) comprising a heterojunction bipolar transistor (HBT 100), the heterojunction bipolar transistor (HBT 100) comprising a sub-collector, a collector, a base and an emitter (Fig. 3);
-a backside contact (Metal 1 and/or with 120 & vias) contacting to the collector; and
-a second chiplet (306, 350) connected to the first chiplet (152, 340), the second chiplet (306, 350) comprising a CMOS device (302, 304) with a frontside contact (e.g. contact above 302, 304) connecting to the heterojunction bipolar transistor (HBT 100).
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Dutta’s Fig. 3 does not explicitly teach a sub-collector, and the backside contact contacting to the sub-collector.
Dutta’s Fig. 1 teaches, [0017-0018], a sub-collector (112), and the backside contact (e.g., 120, 182, 184) contacting to the sub-collector (112).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Dutta’s Fig. 1 to obtain a sub-collector and the backside contact contacts to the sub-collector as claimed, because it aids in allowing for a reduction of base-collector-capacitance (Cbc) of the HBT & improving device power gain.
Re claim 14, Dutta teaches, Fig. 3, [0026], wherein the CMOS device (302, 304) comprises a transistor electrically connecting (e.g. through vias for electrical connection) to the heterojunction bipolar transistor (HBT 100).
Re claim 18, Dutta teaches, under BRI, Fig. 3, [0026, 0030], wherein the backside contact (Metal 1 with vias 320, 322) extends through an insulator material (152) and passivation layer (340) on a backside of the first chiplet (152, 340).
Re claim 19, in combination cited above, Dutta’s Fig. 1 teaches wherein the backside contact (180, 182, 184, 186) connects between a sub-collector (112) of the first device to a redistribution layer (188, 190, 192).
5. Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta in view of Dutta et al. (US 2019/0341381, “Dutta81”).
The teachings of Dutta have been discussed above.
Re claims 4 & 15, Dutta teaches, Fig. 1, a width of the base (104) is greater than a width of the emitter (102).
Dutta does not explicitly teach the width of the base is greater than a width of the collector and a width of the sub-collector.
Dutta81 teaches, Fig. 1, [0019], the width of the base (118) is greater than a width of the collector (120) and a width of the sub-collector (122).
As taught by Dutta81, one of ordinary skill in the art would utilize & modify the above teaching to obtain the width of the base is greater than a width of the collector and a width of the sub-collector as claimed, because it aids in achieving desired dimension of a HBT to provide optimized performance. Further, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dutta81 in combination Dutta due to above reason.
6. Claims 5-7, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta in view of Dutta (US 2020/0266290, “Dutta90”).
The teachings of Dutta have been discussed above.
Re claim 5, Dutta does not explicitly teach a third device connecting to the first device, and third device and the first device comprising a cascode power amplifier.
Dutta90 teaches, Fig. 1, [0018], a third device (108) connecting to the first device (106), and third device (108) and the first device (106) comprising a cascode power amplifier (e.g., formed of two HBT devices).
As taught by Dutta90, one of ordinary skill in the art would utilize & modify the above teaching to obtain a third device connecting to the first device, and third device and the first device comprising a cascode power amplifier as claimed, because it aids in achieving a desired structure with reduced module size and reduced Cbc.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dutta90 in combination Dutta due to above reason.
Re claim 6, in combination cited above, Dutta/Dutta90 does not explicitly teach deep trench isolation structures isolating the first device from the third device.
Dutta90 does teach, Fig. 5, trench isolation structures (520) isolating the first device (502) from the third device (consider 504).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Dutta90 to obtain deep trench isolation structures as claimed, because DTI structure is known in the art, and it aids in improving device reliability and reducing parasitic capacitance.
Re claim 7, in combination cited above, Dutta90 teaches, Fig. 1, [0018], wherein the third device (HBT 108) comprises a heterojunction bipolar transistor with a front side connection to a sub-collector (in 108).
Re claim 16, in combination cited above, Dutta90 teaches, Fig. 1, [0018], a third device (108) connecting to the first device (106), the third device (108) and the first device (106) comprising a cascode power amplifier (e.g., formed of two HBT devices) with the third device (108) comprising a emitter (122, 124) contact through a backside (e.g., via metal 1 & vias).
Re claim 17, in combination cited above, Dutta/Dutta90 does not explicitly teach deep trench isolation structures isolating the first device from the third device.
Dutta90 does teach, Fig. 5, trench isolation structures (520) isolating the first device (502) from the third device (consider 504).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Dutta90 to obtain deep trench isolation structures as claimed, because DTI structure is known in the art, and it aids in improving device reliability and reducing parasitic capacitance.
7. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dutta in view of Zhu et al. (US 2019/0067105).
The teachings of Dutta have been discussed above.
Re claim 11, Dutta does not explicitly teach the wiring structures comprise 3D heterogeneously integrated (3DHI) contact structures.
Zhu teaches the use of 3D integrated wiring structure (abstract).
As taught by Zhu, one of ordinary skill in the art would utilize & modify the above teaching to obtain 3D heterogeneously integrated (3DHI) contact structures as claimed, because it aids in achieving a desired wiring structure that enables wiring through thick device layer at reduced cost.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Zhu in combination Dutta due to above reason.
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 5/7/26
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