Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of invention II in the reply filed on 4/20/2026 is acknowledged.
Claims 1-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/20/2026.
Claim Objections
Claim 25 objected to because of the following informalities:
Claim 2 recites the limitation “The method of claim 24, wherein opening further exposes the source/drain epitaxial structure.” This should read “The method of claim 24, wherein the opening further exposes the source/drain epitaxial structure.”
Appropriate correction is required.
Claim Rejections 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16, 17, 20 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang (US Pub 20230178600), hereinafter referred to as Chuang.
Regarding claim 16, Chuang teaches a method, comprising: forming first semiconductor layers (Chuang, 106a, 108a, Fig. 13A-1, paras. 75, 179) one above another over a substrate (Chuang, 102a, Fig. 13A-1, paras. 75, 179); forming a gate structure (Chuang, 136a, Fig. 13A-1, para. 75, 179) over the first semiconductor layers; etching the first semiconductor layers to form a source/drain opening (Chuang, 150a, Fig. 13A-1, paras. 78, 179); forming an epitaxial layer in the source/drain opening (Chuang, 158a, Fig. 13A-1, paras. 86, 179); forming a dielectric layer covering the epitaxial layer (Chuang, 120a, 164a, Fig. 13B-2, paras. 76, 87, 179); etching back the dielectric layer until a top surface of the epitaxial layer is exposed (Chuang, Fig. 13C-1, para. 183); and forming a source/drain epitaxial structure in the source/drain opening and in contact with the top surface of the epitaxial layer. (Chuang, 168a,Fig. 13D-2, para. 186-187).
Regarding claim 17, Chuang teaches the method of claim 16, wherein portions of the dielectric layer (Chuang, 120a, Fig 13D-2) remain on opposite sides of the epitaxial layer after etching back the dielectric layer.
Regarding claim 20, modified Chuang teaches the method of claim 16, wherein the source/drain epitaxial structure (Chuang, 168a, Fig. 13D-2, paras. 186-187) is in contact with a remaining portion of the dielectric layer (Chuang, 164a, 120a, Fig. 13D02, para. 76).
Regarding claim 22, Chuang teaches the method of claim 16, wherein the epitaxial layer (Chuang, 168a, Fig. 13D-2 protrudes from a remaining portion of the dielectric layer (Chuang, 120a, Fig. 13D-2).
Claim Objection 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 18 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang.
Regarding claim 18, Chuang teaches the method of claim 16, but does not explicitly teach wherein forming the epitaxial layer is performed such that a sidewall of a bottommost one of the first semiconductor layers is covered by the epitaxial layer.
However, Chuang teaches that the thickness of the semiconductor layers may be individually controlled to determine how many of the semiconductor layers remain exposed. This results in the ability to individually adjust the operating characteristics of the transistor (Chuang, para. 115).
Therefore it would have been obvious to modify the transistors of Chuang using the individually controlled thickness of the semiconductor layers of Chuang to create an individually adjustable series of transistors.
Claims 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang as applied to claim 16 above, and further in view of Chang et al., (US Pub 20220367243), hereinafter referred to as Chang.
Regarding claim 24, Chuang teaches the method of claim 16, but does not teach further comprising: etching the epitaxial layer from a backside of the substrate to form an opening exposing the dielectric layer; and forming a via in the opening.
However, Chang teaches an integrated circuit wherein the sacrificial epitaxial plugs (Chang, 180, Fig 21, para. 40) are etched to form openings (Chang, O5, Fig. 22, para. 71) and then forming a via (Chang 292, Fig. 24, para. 74) in the opening.
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the integrated circuit of Chuang with the backside vias of Chang in order to connect to a backside power rial thus allowing for more routing space and hence higher routing density (Chang, para. 99).
Regarding claim 25, modified Chuang teaches the method of claim 24, wherein the opening further exposes the source/drain epitaxial structure (Chang, 192 Fig. 22, para. 47).
Regarding claim 26, modified Chuang teaches the method of claim 25, further comprising forming a silicide layer (Chang, 280, Fig. 24, para. 73) from an exposed surface of the source/drain epitaxial structure prior to forming the via.
Regarding claim 27, modified Chuang teaches the method of claim 26, wherein the silicide layer interfaces with a remaining portion of the dielectric layer.
Examiner’s Note: Given that modified Chuang teaches that the original epitaxial layer passed through the remaining portion of the dielectric layer before being etched away to make the opening, a silicide layer formed in the bottom of the opening would be in contact with the remaining portion of the dielectric layer.
Allowable Subject Matter
Claims 19, 21 and 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 28-35 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 28, Chuang teaches a method, comprising: forming first semiconductor layers (Chuang, 106a, 108b, Fig. 3A-1, para. 75) and second semiconductor layers (Chuang, 106a, 108a, Fig. 3A-1, para. 75) over a substrate; etching the first semiconductor layers and the second semiconductor layers to form a first source/drain (Chuang, 150b, Fig. 3B-1, para. 78) opening in the first semiconductor layers and a second source/drain opening (Chuang, 150a, Fig. 3B-1, para. 78) in the second semiconductor layers; forming a first epitaxial layer (Chuang, 158b, Fig. 3D-1, para. 86) and a second epitaxial layer (Chuang, 158a, Fig. 3D-1, para. 86) in the first source/drain opening and the second source/drain opening, respectively, forming a dielectric layer (Chuang, 164b, para. 93-94, Fig. 3G-1, para. 87) in the first source/drain opening and over the first epitaxial layer; forming a first source/drain structure (Chuang, 168b, Fig. 3L-1, para. 116) in the first source/drain opening; and forming a second source/drain structure (Chuang 168a, Fig. 3L-1, para. 116) in the second source/drain opening.
Chuang does not teach, nor does the prior art suggest wherein a top surface of the first epitaxial layer is higher than a bottommost one of the first semiconductor layers and a top surface of the second epitaxial layer is higher than a bottommost one of the second semiconductor layers; or etching back the second epitaxial layer.
Claims 29-31 are allowed as depending from allowable claim 28.
Regarding claim 32, Chuang teaches a method, comprising: forming first semiconductor layers one above another (Chuang, 106b, 108b, Fig. Fig. 3A-1, para. 75) over a substrate (Chuang, 102b, para. 75); forming a gate structure (Chuang, 136b, Fig. 3A-1, para. 75) over the first semiconductor layers; etching the first semiconductor layers to form a source/drain opening (Chuang, 150b, Fig. 3B-1, para. 78); forming an epitaxial layer (Chuang, 168b, Fig. 3D-1, para. 86) in the source/drain opening, and forming a source/drain epitaxial structure (Chuang, 168b, Fig. 3L-1, para. 116) in the source/drain opening and over the epitaxial layer
Chuang does not teach nor does the prior art suggest wherein the epitaxial layer has a trapezoidal top surface profile.
Claims 33-35 are allowed as depending from allowable claim 32.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (US Pub. 20220367727 teaches a method whereby an epitaxial layer is deposited below the source drain region and later removed to form a backside via.
Yu et al. (US Pub 20070298593) teaches that epitaxial layers are a preferred seed layer for further epitaxial growth.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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