Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-8 and 10-11, in the reply filed on August 17th, 2026, are acknowledged. Claim 1 has been amended. Claims 9 and 12-20 have been cancelled. Claim 21 has been added. Claims 1-8, 10-11 and 21 are pending.
Action on merits of claims 1-8, 10-11 and 21 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Basker (US 2019/0341467, hereinafter as Bask ‘467) in view of Hatcher (US 2016/0172358, hereinafter as Hatc ‘358) and further in view of Cheng (US 2020/0266060, hereinafter as Cheng ‘060).
Regarding Claim 1, Bask ‘467 teaches a semiconductor device, comprising:
a source/drain region (Fig. 2G, (29); [0044]) adjacent to a gate channel (30/32; [0046]);
a plurality of nanosheets (21; [0038]) extended vertically at the gate channel; and
a source/drain extension (SDE) (38; [0031]) between the source/drain region (29) and the plurality of nanosheets, wherein portions of the SDE in vicinity of the source/drain region are doped with a first dopant (see para. [0032]).
Bask ‘467 is shown to teach all the features of the claim with the exception of explicitly the limitations: “each nanosheet of the plurality nanosheets has a middle portion of a first thickness and an end portion having a second thickness located on opposing sides of the middle portion, wherein the second thickness is less than the first thickness”.
Hatc ‘358 teaches each nanosheet (Fig. 2, (150-1); [0043]) of the plurality nanosheets has a middle portion of a first thickness and an end portion having a second thickness located on opposing sides of the middle portion, wherein the second thickness is less than the first thickness.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Bask ‘467 by having a middle portion of a first thickness and an end portion having a second thickness located on opposing sides of the middle portion, wherein the second thickness is less than the first thickness in order to decrease Band to Band Tunneling (BTBT) leakage current in a drain region (see para. [0040]) as suggested by Hatc ‘358.
Bask ‘467 and Hatc ‘358 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the SDE extends above and below each end portion of the plurality of nanosheets”.
Cheng ‘060 teaches the SDE (Fig. 1A, (140); [036]) extends above and below each end portion of the plurality of nanosheets (116; [0036]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Bask ‘467 and Hatc ‘358 by having the SDE extends above and below each end portion of the plurality of nanosheets in order to reduce the parasitic resistance in the end portions of the semiconductor channel layers and increase surface area to serve as a seed for the epitaxial growth of the epitaxial S/D layers (see para. [0041]) as suggested by Cheng ‘060.
Regarding Claim 2, Bask ‘467 teaches the semiconductor device is a nanosheet gate-all-around field-effect transistor (GAA FET) (see Fig. 2G; [0004]).
Regarding Claim 3, Bask ‘467 teaches the plurality of nanosheets (21; [0027]) is made of silicon
Regarding Claim 4, Bask ‘467 teaches the semiconductor device is a p-type field-effect transistor (pFETsee para. [0035]), and the first dopant is a p-type dopant (see para. [0033]), wherein the p-type dopant is Boron (B).
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Fig. 2G (Bask ‘467)
Regarding Claim 5, Bask ‘467 teaches the semiconductor device is an n-type field-effect transistor (nFETsee para. [0035]), and the first dopant (see para. [0033]) is an n-type dopant, wherein the n-type dopant is Phosphorous (P).
Regarding Claim 6, Bask ‘467 teaches the first dopant is a same material as a source/drain region dopant (see para. [0033] and [0035]).
Regarding Claim 7, Bask ‘467 is shown to teach all the features of the claim with the exception of explicitly the limitations: “the first dopant is different from a source/drain region dopant”.
However, it has been held to be within the general skill of a worker in the art to select the first dopant is different from a source/drain region dopant on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to have the first dopant is different from a source/drain region dopant in order to improve the performance of the semiconductor device.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bask ‘467, Hatc ‘358 and Cheng ‘060 as applied to claim 1 above, and further in view of Chang (US 2018/0047853, hereinafter as Chang ‘853).
Regarding Claim 8, Bask ‘467, Hatc ‘358 and Cheng ‘060 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the doped portions of the SDE are doped with a drive-in anneal along a direction orthogonal to the gate channel”.
Chang ‘853 teaches the doped portions of the SDE are doped with a drive-in anneal along a direction orthogonal to the gate channel (see Fig. 8A, para. [0018]-[0019] and [0060]-[0061]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Bask ‘467 to have the doped portions of the SDE are doped with a drive-in anneal along a direction orthogonal to the gate channel for the purpose of providing a sharp source/drain junction (see para. [0060]) as suggested by Chang ‘853.
Product by process limitation:
The expression “doped with a drive-in anneal” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Bask ‘467, Hatc ‘358 and Cheng ‘060 as applied to claim 9 above, and further in view of Palle (US 2017/0271477, hereinafter as Pall ‘477).
Regarding Claim 10, Bask ‘467, Hatc ‘358 and Cheng ‘060 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a first layer encapsulating each of the plurality of nanosheets”.
Pall ‘477 teaches a first layer (interfacial layer; Fig. 3H, (323); [0039]) encapsulating each of the plurality of nanosheets (309; [0030]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Bask ‘467, Hatc ‘358 and Cheng ‘060 to have a first layer encapsulating each of the plurality of nanosheets for the purpose of forming a gate stack (see para. [0039]) as suggested by Pall ‘477.
Regarding Claim 11, Bask ‘467, Hatc ‘358, Cheng ‘060 and Pall ‘477 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the first layer is made of silicon or silicon germanium”.
However, it has been held to be within the general skill of a worker in the art to select silicon or silicon germanium for the first layer material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (See Fig. 3 of US 2019/0198645; as evidence);
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A person of ordinary skills in the art is motivated to select silicon or silicon germanium for the first layer material in order to improve the performance of the semiconductor device.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Basker (US 2019/0341467, hereinafter as Bask ‘467) in view of Hatcher (US 2016/0172358, hereinafter as Hatc ‘358).
Regarding Claim 21, Bask ‘467 teaches a semiconductor device, comprising:
a source/drain region (Fig. 2G, (29); [0044]) adjacent to a gate channel (30/32; [0046]);
a plurality of nanosheets (21; [0038]) extended vertically at the gate channel; and
a source/drain extension (SDE) (38; [0031]) between the source/drain region (29) and the plurality of nanosheets, wherein portions of the SDE in vicinity of the source/drain region are doped with a first dopant (see para. [0032]); and the SDE (38; [0031]) has a tapered profile.
Bask ‘467 is shown to teach all the features of the claim with the exception of explicitly the limitations: “the SDE has a tapered profile in which a thickness of the SDE decreases from an interface with the each of the nanosheets of the plurality of nanosheets”.
Hatc ‘358 teaches the SDE (Fig. 20, (400-2); [0053]) has a tapered profile in which a thickness of the SDE decreases from an interface with the each of the nanosheets (150-2; [0052]) of the plurality of nanosheets.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Bask ‘467 by having the SDE has a tapered profile in which a thickness of the SDE decreases from an interface with the each of the nanosheets of the plurality of nanosheets in order to decrease Band to Band Tunneling (BTBT) leakage current in a drain region (see para. [0040]) as suggested by Hatc ‘358.
Further, it has been held to be within the general skill of a worker in the art to select the SDE has a tapered profile in which a thickness of the SDE decreases from an interface with the each of the nanosheets of the plurality of nanosheets on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to have the SDE has a tapered profile in which a thickness of the SDE decreases from an interface with each of the nanosheets of the plurality of nanosheets in order to improve the performance of the semiconductor device.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraph numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
Applicant’s arguments with respect to claims 1-8, 10-11 and 21, filed on August 17th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893
