DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Graphene, siliver US 20190139902 A1
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (U.S. Pub #2019/0139902).
With respect to claim 1, Lee teaches a chip package with heat dissipation and electromagnetic protection comprising:
a package unit (Fig. 1, 10) which includes a substrate (Fig. 1, 200), at least one first circuit layer (Fig. 1, 202 and Paragraph 38), at least one second circuit layer (Fig. 1, 201), at least one die (Fig. 1, 100b), and an insulating layer (Fig. 1, insulating layer of substrate 200; Paragraph 39; or Fig 1, 300b and Paragraph 40);
wherein the substrate is provided with a first surface (Fig. 1, top surface of 200) and a second surface (Fig. 1, bottom surface of 200) opposite to the first surface;
wherein the first circuit layer is disposed on the first surface of the substrate and provided with a first surface;
wherein the second circuit layer is arranged at the second surface of the substrate and electrically connected with the first circuit layer;
wherein the die is mounted on the first surface of the first circuit layer by flip chip and composed of a front surface electrically connected with the first circuit layer correspondingly and a back surface opposite to the front surface; wherein the insulating layer is disposed on the substrate and covering the die while the back surface of the die is exposed;
wherein a top portion of the package unit is formed by grinding an original top of the package unit with grinding technique and a level of the back surface of the die is the same with a level of the top portion of the package unit after the grinding (Fig. 4 and Paragraph 47); and
a heat dissipation shielding layer (Fig. 1, 301a and Paragraphs 41-42) which is completely covering the top portion of the package unit for providing functions of electromagnetic protection and heat dissipation to the package unit specifically;
wherein a method of manufacturing the chip package includes the following steps:
Step S1: (Fig. 2-3) providing a support board with a plurality of package units each of which includes a substrate, at least one first circuit layer, at least one second circuit layer, at least one die, and an insulating layer; wherein the substrate consists of a first surface and a second surface opposite to each other; wherein the first circuit layer is disposed on the first surface of the substrate and provided with a first surface; wherein the second circuit layer is arranged at the second surface of the substrate and electrically connected with the first circuit layer; wherein the die is mounted on the first surface of the first circuit layer by flip chip and provided with a front surface electrically connected with the first circuit layer; wherein the insulating layer is disposed on the substrate and covering the die while a top of the insulating layer forms an original top of the package unit;
Step S2: using grinding technique to grind the original top of the package unit until a back surface of the die is exposed and forming a top portion of the package unit at a level lower than the original top after the grinding; wherein a level of the back surface of the die is the same with the level of the top portion of the package unit (Fig. 4 and Paragraph 47);
Step S3: covering the top portion of the package unit with a heat dissipation shielding layer completely (Fig. 6); and
Step S4: dividing the respective chip packages from the support board to get individual chip packages (Fig. 7 and Paragraph 50).
Regarding the set of limitations indented under ‘wherein a method of manufacturing the chip package includes the following steps:” and including steps S1-S4 it noted that the claim has been drafted statutorily as a device claim;
note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Fitzgerald, 205 USPQ 594, 596 (CCPA); In re Marosi et al., 218 USPQ 289 (CAFC); and most recently, In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) all of which make it clear that it is the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has burden of proof in such cases as the above case law makes clear.
As to the grounds of rejection, see MPEP § 2113 section 1.
With respect to claim 2, Lee teaches the die further includes an original back surface (Fig. 3, 100a);
wherein the back surface of the die is formed by the grinding in the step S2 of the original back surface so that the level of the back surface of the die is lower than a level of the original back surface (Fig. 4, 100b).
With respect to claim 6, Lee teaches that the heat dissipation shielding layer is formed by silver adhesive coating or graphene coating (Paragraph 41).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Mallik et al (U.S. Pub #2020/0273811).
With respect to claim 3, Lee does not teach that a thickness of the die is equal or close to 20 micrometer (um) after formation of the back surface of the die by the grinding in the step S2.
Mallik teaches a thickness of a die that equal or close to 20 micrometer (um) (Fig. 1A, 110, T1; Paragraph 30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the die of Lee to have a thickness of equal or close to 20 um as taught by Mallik in order to achieve the predictable result of provide a flip chip device package.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Jusket et al (U.S. Patent #9269887).
With respect to claim 4, Lee does not teach that a thickness of the package unit is 0.4 mm - 1.0 mm and the thickness of the package unit is further reduced to 0.15 mm - 0.3 mm after the grinding.
Juskey teaches a thickness of the package unit is further reduced to 0.15 mm - 0.3 mm (Col 7 Ln 31-36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the chip and substrate of Lee such that the package thickness is 0.15-0.3 mm as taught by Juskey in order to produce a thin package (Col 1 Ln 31-35).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of DiManno Jr. et al (U.S. Pub #2019/0051614).
With respect to claim 5, Lee does not teach that the heat dissipation shielding layer is formed by copper electroplating or nickel gold electroplating.
DiManno teaches a heat dissipation shielding layer is formed by copper electroplating or nickel gold electroplating (Paragraph 57).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the shielding layer of Lee by copper electroplating or nickel gold electroplating as taught by DiManno in order to achieve the predictable result of provide the shielding layer over the chip and encapsulation materials.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Scanlan (U.S. Pub #2017/0084596).
With respect to claim 7, Lee does not teach that the heat dissipation shielding layer is formed by direct adhesion of a heat sink.
Scanlan teaches a heat dissipation shielding layer is formed by direct adhesion of a heat sink (Fig. 3K, 226 ; or Fig. 4, 242).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a heat sink by direct adhesion as the heat dissipation shielding layer of Lee as taught by Scanlan in order to improve the thermal performance of the structure (Paragraph 74).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, in view of Chen et al (U.S. Pub #2014/0061903).
With respect to claim 8, Lee does not teach that the first surface of the substrate is further provided with at least one blind hole and the first circuit layer disposed on the first surface of the substrate is extending to a surface of an inner wall of the blind hole of the substrate; thereby the first circuit layer is electrically connected with the second circuit layer due to extension of the first circuit layer on the blind hole of the substrate.
Chen teaches a first surface of the substrate is further provided with at least one blind hole (Fig. 4, 218 and Paragraph 29) and the first circuit layer (Fig. 4, 212) disposed on the first surface of the substrate is extending to a surface of an inner wall of the blind hole of the substrate;
thereby the first circuit layer is electrically connected with the second circuit layer (Fig. 4, 213) due to extension of the first circuit layer on the blind hole of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the substrate of Lee to comprise at least one blind hold as taught by Chen in order to achieve the predictable result of making an electrical connection between the first circuit layer and second circuit layer.
Conclusion
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/BENJAMIN P SANDVIK/ Primary Examiner, Art Unit 2812
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