DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 recites the limitation "the CSP pad" in line 3. There is insufficient antecedent basis for this limitation in the claim. NOTE: Neither claim 1 or claim 6 mentions “a CPS pad”. In claim 3, the Applicant claims a chip scale package (CSP) pad (recited in line 8). Thus, the Examiner suggests either to amend the dependency of claim 7 to be depended on claim 3.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,5 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tseng (US 2013/008705).
Regarding claim 1, Tseng teaches a package substrate in fig. 4’, comprising:
a dielectric layer structure (24/220) including a first dielectric layer (refer to lowermost dielectric layer 220) and a second dielectric layer (refer to uppermost dielectric 220);
a plurality of bonding pads (21) located at a lower surface of the first dielectric layer (18/20);
a plurality of metal pillars (see notation below or refer to 23 labelled in fig.3 ) located on an upper surface of the second dielectric layer (refer to uppermost 220); and
a metal interconnect structure (221) extending from the plurality of bonding pads (21) to the plurality of metal pillars (23 as labelled in fig. 3) and including a plurality of first metal vias (refer to lowermost 222) in the first dielectric layer (refer to lowermost dielectric 220) and a plurality of second metal vias (refer to uppermost via 222) in the second dielectric layer (refer to uppermost dielectric 220), wherein the plurality of first metal vias (refer to lowermost 222) and the plurality of second metal vias (refer to uppermost 222) have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer (see fig. 4’).
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Regarding claim 5, Tseng teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 3 of Tseng teaches the plurality of bonding pads (21) are embedded in the first dielectric layer (refer to lowermost 220).
Regarding claim 10, Tseng teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 4’ of Tseng shows the plurality of second metal vias (refer to uppermost 222) comprises a plurality of uppermost second metal vias (refer to uppermost 222) located at the upper surface of the second dielectric layer (refer to uppermost dielectric 220), and the plurality of uppermost second metal vias (refer to uppermost 222) have a substantially uniform cross-sectional diameter.
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Claims 1, 10, 11 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2022/0077066).
Regarding claim 1, Kim teaches a package substrate in fig. 11, comprising:
a dielectric layer structure (100) including a first dielectric layer (refer to a lowermost dielectric layer 111) and a second dielectric layer (refer to an uppermost dielectric 115);
a plurality of bonding pads (150) located at a lower surface of the first dielectric layer (refer to lower surface 100b);
a plurality of metal pillars (140) located on an upper surface of the second dielectric layer (refer to upper surface of 115 or 100a); and
a metal interconnect structure (refer to redistribution patterns 120/130) extending from the plurality of bonding pads (150) to the plurality of metal pillars (refer to 140) and including a plurality of first metal vias (refer to metal vias of 130 and 120) in the first dielectric layer (refer to lowermost dielectric 111) and a plurality of second metal vias (refer to uppermost via 130) in the second dielectric layer (refer to uppermost dielectric 115), wherein the plurality of first metal vias (refer to lowermost 222) and the plurality of second metal vias (refer to uppermost 222) have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer (see fig.11).
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Regarding claim 10, Kim teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Kim teaches the plurality of second metal vias comprises a plurality of uppermost second metal vias located at the upper surface of the second dielectric layer, and the plurality of uppermost second metal vias have a substantially uniform cross-sectional diameter.
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Regarding claim 11, Kim teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Kim teaches the plurality of uppermost second metal vias are connected to the plurality of metal pillars, respectively, and the cross-sectional diameter of the plurality of uppermost second metal vias is substantially the same as a cross-sectional diameter of the plurality of metal pillars.
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Regarding claim 14, Kim teaches a method of forming a package substrate in fig.11, the method comprising:
forming a plurality of bonding pads (150) on a carrier substrate (800);
forming a dielectric layer structure (110) on the plurality of bonding pads (150), wherein the dielectric layer structure includes a first dielectric layer (111) and a second dielectric layer (115);
forming a metal interconnect structure (see notation below) including a plurality of first metal vias in the first dielectric layer (111) and a plurality of second metal vias in the second dielectric layer (115), wherein the plurality of first metal vias and the plurality of second metal vias have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer (see fig. 11); and
forming a plurality of metal pillars (140) on an upper surface of the second dielectric layer (refer to uppermost dielectric layer 115), wherein the metal interconnect structure extends from the plurality of bonding pads (150) to the plurality of metal pillars (140) (see notation below).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tseng (US 2013/0008705) as applied to claim 1 above, and further in view of Furuichi (US 2012/0234589).
Regarding claim 2, Tseng teaches all the limitations of the claimed invention for the same reasons as set forth above except for a solder resist layer on the lower surface of the first dielectric layer, wherein a surface of the plurality of bonding pads is exposed through the solder resist layer.
Furuichi teaches the same field of an endeavor wherein a solder resist layer (22) on the lower surface of the first dielectric layer (22), wherein a surface of the plurality of bonding pads (21P) is exposed through the solder resist layer (22).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a solder resist layer on the lower surface of the first dielectric layer, wherein a surface of the plurality of bonding pads is exposed through the solder resist layer as taught by Furuichi in the teaching of Tseng in order to protect the wiring substrate (see par. 43).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tseng (US 2013/0008705) as applied to claim 1 above, and further in view of Ogawa (US 2010/0065322).
Regarding claim 12, Tseng teaches all the limitations of the claimed invention for the same reasons as set forth above except for the lower surface of the first dielectric layer includes a plurality of recessed portions and the plurality of bonding pads are located in the plurality of recessed portions, respectively.
Ogawa teaches the same field of the endeavor wherein the lower surface of the first dielectric layer (12) includes a plurality of recessed portions (refer to bottom recesses at lower surface of 12) and the plurality of bonding pads (refer to 41P) are located in the plurality of recessed portions (refer to recesses at the lower surface of 12), respectively (see fig. 5 and par. 69).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the lower surface of the first dielectric layer includes a plurality of recessed portions and the plurality of bonding pads are located in the plurality of recessed portions, respectively as taught by Ogawa in the teaching of Tseng in order to reduce an overall size of the package.
Claims 6,8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0077066) as applied to claim 1 above, and further in view of Yew (US 20230395519).
Regarding claim 6, Kim teaches all the limitations of the claimed invention for the same reasons as set forth above except for the plurality of bonding pads comprises a lower two-dimensional identification (2DID) pad on the lower surface of the first dielectric layer.
Yew teaches the same field of an endeavor wherein the plurality of bonding pads comprises a lower two-dimensional identification (2DID) pad (115) on the lower surface of the first dielectric layer (refer to one of the dielectric layer of 103) (see fig. 7A and 7B).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the plurality of bonding pads comprises a lower two-dimensional identification (2DID) pad on the lower surface of the first dielectric layer as taught by Kwang in the teaching of Kim so that the uniformity of the bonding pads provides the efficient and reliable connection for the package device.
Regarding claim 8, Kim teaches all the limitation of claimed invention for the same reasons as set forth above except for the plurality of bonding pads comprises: a plurality of ball grid array (BGA) bonding pads at the lower surface of the first dielectric layer; and a lower surface-mounted device (SMD) pad located at the lower surface of the first dielectric layer.
Yew teaches the same field of an endeavor wherein the plurality of bonding pads comprises: a plurality of ball grid array (BGA) bonding pads (207) at the lower surface of the first dielectric layer (refer to lower surface of 103); and a lower surface-mounted device (SMD) pad (113) located at the lower surface of the first dielectric layer (refer to lower surface of 103) (see fig. 12).
Thus, it would have been obvious to one having ordinary skill in the art before the invention was made to include the plurality of bonding pads comprises: a plurality of ball grid array (BGA) bonding pads at the lower surface of the first dielectric layer; and a lower surface-mounted device (SMD) pad located at the lower surface of the first dielectric layer as taught by Yew in the teaching of Kim in order to provide an electrical connection between the interposer of the package structure and the package substrate and also reduce the height of the package structure by having a lower surface mounted device (SMD) pad.
Regarding claim 9, Kim teaches all the limitation of claimed invention for the same reasons as set forth above except for the plurality of first metal vias comprises a plurality of lowermost first metal vias located at the lower surface of the first dielectric layer, and the plurality of lowermost first metal vias comprises a lower surface-mounted device (SMD) pad.
Yew teaches the same field of an endeavor the plurality of first metal vias comprises a plurality of lowermost first metal vias located at the lower surface of the first dielectric layer, and the plurality of lowermost first metal vias (refer to lowermost metal vias of interposer 103) comprises a lower surface-mounted device (SMD) pad (113) (see fig. 12).
Thus, it would have been obvious to one having ordinary skill in the art before the invention was made to include the plurality of bonding pads comprises: a plurality of ball grid array (BGA) bonding pads at the lower surface of the first dielectric layer; and a lower surface-mounted device (SMD) pad located at the lower surface of the first dielectric layer as taught by Yew in the teaching of Kim in order to provide an electrical connection between the interposer of the package structure and other device at the lower surface of the interposer.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0077066) as applied to claim 14 above, and further in view of Furuichi (US 2012/0234589).
Regarding claim 15, Kim teaches all the limitations of the claimed invention for the same reasons as set forth above except for a solder resist layer on the lower surface of the first dielectric layer, wherein a surface of the plurality of bonding pads is exposed through the solder resist layer.
Furuichi teaches the same field of an endeavor wherein a solder resist layer (22) on the lower surface of the first dielectric layer (22), wherein a surface of the plurality of bonding pads (21P) is exposed through the solder resist layer (22).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a solder resist layer on the lower surface of the first dielectric layer, wherein a surface of the plurality of bonding pads is exposed through the solder resist layer as taught by Furuichi in the teaching of Kim in order to protect the wiring substrate (see par. 43).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2022/0077066) as applied to claim 1 above, and further in view of Yew (US 20230395519).
Regarding claim 19, Kim teaches all the limitations of the claimed invention for the same reasons as set forth above except for the forming of the plurality of bonding pads comprises: forming a plurality of ball grid array (BGA) bonding pads at a lower surface of the first dielectric layer; forming a lower two-dimensional identification (2DID) pad adjacent the plurality of BGA bonding pads at the lower surface of the first dielectric layer; and forming a lower surface-mounted device (SMD) pad adjacent the plurality of BGA bonding pads at the lower surface of the first dielectric layer.
Yew teaches the same field of an endeavor wherein the forming of the plurality of bonding pads comprises: forming a plurality of ball grid array (BGA) bonding pads (115) at a lower surface of the first dielectric layer; forming a lower two-dimensional identification (2DID) pad adjacent the plurality of BGA bonding pads at the lower surface of the first dielectric layer; and forming a lower surface-mounted device (SMD) pad (113) adjacent the plurality of BGA bonding pads (115) at the lower surface of the first dielectric layer (see fig. 12).
Thus, it would have been obvious to one having ordinary skill in the art before the invention was made to include the forming of the plurality of bonding pads comprises: forming a plurality of ball grid array (BGA) bonding pads at a lower surface of the first dielectric layer; forming a lower two-dimensional identification (2DID) pad adjacent the plurality of BGA bonding pads at the lower surface of the first dielectric layer; and forming a lower surface-mounted device (SMD) pad adjacent the plurality of BGA bonding pads at the lower surface of the first dielectric layer as taught by Yew in the teaching of Kim in order to provide an electrical connection between the interposer of the package structure and other device at the lower surface of the interposer.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 2023/0386945), and further in view of Kim (US 2022/0077066).
Regarding claim 20, Hung teaches a package structure (in fig. 19) comprising:
a package substrate (200), comprising: a dielectric layer structure (refer to dielectric layers 242/210/262) including a first dielectric layer (refer to the lowermost dielectric layer 242) and a second dielectric layer (refer to uppermost dielectric layer 262);
a plurality of ball grid array (BGA) bonding pads (248) located at a lower surface of the first dielectric layer (refer to lower surface of the lowermost dielectric layer 242);
a plurality of metal pillars (268 and 290) located on an upper surface of the second dielectric layer (refer to upper surface of the uppermost dielectric layer 262), wherein the plurality of metal pillars (268 and 290) comprises a plurality of C4 metal bumps (290; see par. 70) and a plurality of chip-scale package pads (268); and
a metal interconnect structure (264/244) extending from the BGA bonding pads (248) to the plurality of metal pillars (290) and a plurality of first metal vias (refer to via at wiring 244) in the first dielectric layer (refer to lowermost dielectric layer 242) and a plurality of second metal vias (refer to vias at wiring 262) in the second dielectric layer (refer to the uppermost dielectric layer 262);
an interposer module (900) on the plurality of C4 metal bumps (290), wherein the interposer module includes an interposer (900) and a plurality of semiconductor devices (810) on the interposer (900), and wherein the plurality of semiconductor devices (810) are electrically coupled to the BGA bonding pads (248) through the metal interconnect structure (264/244);
a chip-scale package (701) on the plurality of chip-scale package pads (268) and electrically coupled to the BGA bonding pads (248) through the metal interconnect structure (264/244); and
a package lid (294) located over the interposer module (900) and the chip-scale package (701) and including a package lid foot portion (293) attached to the package substrate (200).
Hung does not teach metal interconnect structure including the plurality of first metal vias and the plurality of second metal vias have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer.
Kim teaches the same field of an endeavor wherein the plurality of first metal vias and the plurality of second metal vias have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer (see fig. 11’s notation below; see par. 32).
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Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the plurality of first metal vias and the plurality of second metal vias have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer as taught by Kim in the teaching of Hung in order to improve reliability and electrical characteristics against thermal stress may be provided or realized (see par. 40).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “…; a metal dam adjacent the plurality of C4 metal bumps on the upper surface of the second dielectric layer; and a chip-scale package (CSP) pad adjacent the metal dam on the upper surface of the second dielectric layer, wherein a diameter of the CSP pad is greater than a diameter of the plurality of C4 metal bumps” in combination of all of the limitations of claim 3. Claim 4 includes all of the limitations of claim 3.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “at least one of the first dielectric layer or the second dielectric layer comprises at least one of glass fibers or ceramic fibers embedded in an organic material matrix” in combination of all of the limitations of claim 13.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “…; forming a metal dam adjacent the plurality of C4 metal bumps on the upper surface of the second dielectric layer; and forming a chip-scale package (CSP) pad adjacent the metal dam on the upper surface of the second dielectric layer, wherein a diameter of the CSP pad is greater than a diameter of the plurality of C4 metal bumps” in combination of all of the limitations of claim 16. Claim 17-18 includes all of the limitations of claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818