DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II (claims 9-20) in the reply filed on 18 July 2026 is acknowledged. Claims 1-8 (drawn to non-elected Invention I) are withdrawn from consideration.
Claim Objections
Claim 15 objected to because of the following informalities. Claim 15 recites the limitation “forming a trench through a backside of a substrate of with a trench opening” in lines 2-3 of the claim. For the purpose of this office action, the limitation is interpreted to have the following meaning: forming a trench through a backside of a substrate with a trench opening. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 14, 15, 20, 21, and 26 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 10-14 are rejected as they include the limitations of independent claim 9 on which they depend, claims 16-20 are rejected as they include the limitations of independent claim 15 on which they depend, and claims 22-28 are rejected as they include the limitations of independent claim 21 on which they depend.
Claim 9 recites the limitation, "forming a uniform isolation layer on the first portion of the sidewalls of the trench by flowing a fluid into the trench that forms the isolation layer on the first portion of the sidewalls of the trench, does not form the isolation layer on the second portion or the base of the trench," in lines 7-9 of the claim. The metes and bounds of the scope of this limitation are unclear, as it is unclear if “the isolation layer” of line 8 is referring to the “uniform isolation layer” of line 7, or if this is a distinct isolation layer. The metes and bounds of the scope of this limitation are further unclear, as the phrase, “sidewalls of the trench, does not form the isolation layer on the second portion or base of the trench,” is unclear. It is unclear what feature does not form the isolation on the second portion or the base of the trench. Claim 9 also recites the limitation, “forming a backside via in the trench that includes a conducting material,” in line 11 of the claim. The metes and bounds of the scope of this limitation are unclear, as it is unclear which feature includes the conducting material. It is unclear whether a backside via or the trench includes the conducting material.
Claim 14 recites the limitation, "removing the second masking layer after forming the backside via by a chemical mechanical polishing process," in lines 11-12 of the claim. The metes and bounds of the scope of this limitation are unclear, as it is unclear if the backside via is formed by a chemical mechanical polishing process, or if the second masking layer is removed by a chemical mechanical polishing process. For the purpose of this office action, the limitation is interpreted to have the following meaning: removing the second masking layer by a chemical mechanical polishing process after forming the backside via.
Claim 15 recites the limitation, " flowing a fluid into the trench that forms a uniform isolation layer on the first portion of the sidewalls of the trench and on the base of the trench, and does not form the isolation layer on the second portion of the sidewalls of the trench," in lines 7-9 of the claim. The metes and bounds of the scope of this limitation are unclear, as it is unclear if “the isolation layer” of line 8 is referring to the “uniform isolation layer” of line 7, or if this is a distinct isolation layer. Claim 15 also recites the limitation, “forming a backside via in the trench that includes a conducting material,” in line 12 of the claim. The metes and bounds of the scope of this limitation are unclear, as it is unclear which feature includes the conducting material. It is unclear whether a backside via or the trench includes the conducting material.
Claim 20 recites the limitation, "removing the second masking layer after forming the backside via by a chemical mechanical polishing process," in lines 10-11 of the claim. The metes and bounds of the scope of this limitation are unclear, as it is unclear if the backside via is formed by a chemical mechanical polishing process, or if the second masking layer is removed by a chemical mechanical polishing process. For the purpose of this office action, the limitation is interpreted to have the following meaning: removing the second masking layer by a chemical mechanical polishing process after forming the backside via.
Claim 21 recites the limitation, “forming a backside via in the trench that includes a conducting material,” in line 11 of the claim. The metes and bounds of the scope of this limitation are unclear, as it is unclear which feature includes the conducting material. It is unclear whether a backside via or the trench includes the conducting material.
Claim 26 recites the limitation, "removing the second masking layer after forming the backside via by a chemical mechanical polishing process," in lines 11-12 of the claim. The metes and bounds of the scope of this limitation are unclear, as it is unclear if the backside via is formed by a chemical mechanical polishing process, or if the second masking layer is removed by a chemical mechanical polishing process. For the purpose of this office action, the limitation is interpreted to have the following meaning: removing the second masking layer by a chemical mechanical polishing process after forming the backside via.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US PGPub 20210376155 A1; hereinafter referred to as "Chang”) in view of Kobayashi et al. (US 10546863 B1; hereinafter referred to as "Kobayashi”) and Guha et al. (US PGPub 20200044087 A1; hereinafter referred to as "Guha”).
Re claim 9: Chang teaches a method comprising: forming a trench (FIG. 26C: el. 128; para. 92) through a backside of a substrate (FIG. 26C: el. 50; para. 92) with a trench opening (FIG. 26C: el. 128; para. 92) on the backside of the substrate (FIG. 26C: el. 50; para. 92), wherein a first portion of sidewalls of the trench is formed of first material (FIG. 26C: el. 50; para. 16|first portion of sidewalls formed of silicon substrate), a second portion of the sidewalls of the trench is formed of a second material that is different from the first material (FIG. 26C: el. 125; para. 91| second portion of sidewalls formed of silicon oxide dielectric), and a base of the trench is formed of third material that is different from the first material and the second material (FIG. 26C: el. 92; para. 54); and forming a backside via in the trench that includes a conducting material that is exposed at the backside of the substrate, extends through the substrate, and electrically couples with a source/drain structure (FIG. 27D: el. 130; para. 96). Chang fails to teach forming a uniform isolation layer on the first portion of the sidewalls of the trench by flowing a fluid into the trench that forms the isolation layer on the first portion of the sidewalls of the trench, does not form the isolation layer on the second portion or the base of the trench.
In a similar field of endeavor, Kobayashi teaches treating sidewalls of a via trench by forming a uniform isolation layer on the first portion of the sidewalls of the trench (FIG. 4: el. 30, 22; col. 2: line 31-38|silicon oxide isolation layer 30 formed on first portion 22 of sidewalls, which is a silicon portion of the sidewalls) by flowing a fluid into the trench that forms the isolation layer on the first portion of the sidewalls of the trench (col. 2: lines 31-38| silicon oxide isolation layer 30 formed by an ashing process which is a process of flowing an oxygen containing fluid over the treated surface), does not form the isolation layer on the second portion (FIG. 4: el. 20, 24; col. 2: lines 13-18| isolation layer 30 is not formed on the second portion (20, 24) of the sidewalls of the trench, which is a silicon oxide layer). Kobayashi also teaches a benefit of forming an isolation layer on a first portion of the sidewalls of a trench is an increase in the diffusion barrier between silicon sidewalls of the trench and conductive material of a via formed in the trench while maximizing a width of the conductive fill of the trench (col. 3: lines 31-53). Kobayashi fails to teach does not form the isolation layer on the base of the trench.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Chang and Kobayashi, to enable using the formation of an isolation layer on a portion of a sidewall of a trench of Kobayashi in the method of Chang, for the benefit of increasing the resistance to diffusion of conductive fill materials into semiconductor sidewall materials while maintaining a maximized width and contact area of the conductive fill.
The combination of Chang and Kobayashi fails to disclose does not form the isolation layer on the base of the trench.
In a similar field of endeavor, Guha teaches forming a gate-all-around transistor (FIG. 10A; para. abstract) with a silicon oxide source/drain insulating layer (FIG. 10A: el. 351; para. 61-62) between the source/drain and the semiconductor substrate (FIG. 10A: el. 351, 360, 300). Guha teaches a benefit of the insulating layer between the source/drain and the semiconductor substrate is a reduction in leakage currents in the area below the gates and source/drain (para. 34).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Chang and Kobayashi with the teachings of Guha, to enable using the insulating layer between the source/drain region and the substrate of Guha in the method of the combination of Chang and Kobayashi, for the benefit of reduced leakage currents in the area of the semiconductor substrate adjacent to the gates and source/drain regions.
The combination of Chang, Kobayashi, and Guha teaches flowing a fluid into the trench that forms the isolation layer on the first portion of the sidewalls of the trench (Kobayashi - col. 2: lines 31-38| silicon oxide isolation layer formed on silicon portion of the sidewalls of the trench by an ashing process which is a process of flowing an oxygen containing fluid over the treated surface), does not form the isolation layer on the second portion (Kobayashi - FIG. 4: el. 20, 24; col. 2: lines 13-18| silicon oxide isolation layer is not formed on the second portion of the sidewalls of the trench because the second portion is already a silicon oxide layer) or the base of the trench (Chang – FIG. 26C: el. 128, 50, 92, Guha – Fig. 10A: el. 351, 360, 300| Chang teaches forming a trench in the backside of the substrate 50 to a depth of a material 92 of the source/drain area, which is adjacent to the substrate 50; Guha teaches a silicon oxide source/drain insulating layer 351 as the material of the source/drain area adjacent to the substrate 300; the combination teaches wherein the isolation layer is not formed on the base of the trench, as the base of the trench is formed of a silicon oxide source/drain insulating layer and is already formed of silicon oxide).
Re claim 10: The combination of Chang, Kobayashi, and Guha teaches the method of claim 9, wherein the first material is silicon (Chang - FIG. 26C: el. 50; para. 16|first material of first portion of sidewalls formed of silicon substrate) and the isolation layer is formed of a dielectric material that includes an oxide of silicon (SiOx) or a nitride of silicon (SiNx) (Kobayashi - FIG. 4: el. 30; col. 2: line 31-38|isolation layer 30 formed of silicon oxide).
Re claim 12: The combination of Chang, Kobayashi, and Guha teaches the method of claim 9, wherein the trench has a width in a range of between 5 and 30 nanometers (Chang - FIG. 26D: el. W8; para. 94| Chang specifically discloses that the width is between 20 and 70 nanometers, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”).
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Kobayashi and Guha as applied to claim 9 above, and further in view of Hsiung et al. (US PGPub 20220102511 A1; hereinafter referred to as "Hsiung”).
Re claim 11: The combination of Chang, Kobayashi, and Guha teaches the method of claim 9, but is silent on the thickness of the isolation layer and therefore is silent on wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers.
In a similar field of endeavor, Hsiung teaches a method of forming a trench in a backside of a substrate to connect to a source/drain region of a gate-all-around transistor wherein an oxide isolation layer is formed on a first portion of the trench and not formed on a second portion of the trench, and teaches a functional range of thicknesses of the oxide isolation layer for use in this structure (FIG. 15A, 16A; para. 10, 48). Hsuing teaches wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers (para. 48| Hsuing specifically discloses that the thickness is from about 1 nm to about 3 nm, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Hsiung also teaches a benefit of providing an oxide isolation layer of this thickness is control of the sidewall etching profile with respect to the bottom of the trench and reduced leakage (para. 48, 125).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Chang, Kobayashi, and Guha with the teachings of Hsiung, to enable using isolation layer thickness of Hsiung in the method of the combination of Chang, Kobayashi, and Guha, for the benefit of simplifying manufacturing by using a known feature thickness for successfully integrating isolation layers into backside source/drain trenches of gate-all-around transistors, the benefit of reduced leakage, as well as the benefit of sidewall profile control.
Re claim 13: The combination of Chang, Kobayashi, and Guha teaches the method of claim 9, but is silent on wherein forming the isolation layer includes flowing the fluid at a flow rate in a range of 1 and 20 sccm while providing a pressure in a range of 10 and 100 torr at a power in a range of 500 to 2000 watts for a time in a range of 60 to 360 seconds.
In a similar field of endeavor, Hsiung teaches a method of forming a trench in a backside of a substrate to connect to a source/drain region of a gate-all-around transistor wherein an oxide isolation layer is formed on a first portion of the trench and not formed on a second portion of the trench, and teaches process parameters for the formation of the oxide isolation layer (FIG. 15A, 16A; para. 10, 46-48). Hsuing teaches a power in a range of 500 to 2000 watts (para. 48| Hsiung specifically discloses that the power is 50 to 1000 watts, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Hsiung fails to directly disclose the range of the flow rate, pressure, and time, but teaches processing parameters as result-effective variables for controlling the thickness and uniformity of the isolation layer (para. 46-48). Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the well-known result-effective variables of flow rate, pressure, and time, to achieve the claimed range, as a matter of routine optimization for the benefit of forming an isolation layer with a desired thickness and uniformity.
Claim 15-16, 18, 21-22, 24, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Kobayashi.
Re claim 15: Chang teaches a method comprising: forming a trench (FIG. 26C: el. 128; para. 92) through a backside of a substrate (FIG. 26C: el. 50; para. 92) with a trench opening (FIG. 26C: el. 128; para. 92) at the backside of the substrate (FIG. 26C: el. 50; para. 92), wherein a first portion of sidewalls of the trench is formed of first material (FIG. 26C: el. 50; para. 16|first portion of sidewalls formed of silicon substrate), at least a second portion of the sidewalls of the trench is formed of a second material that is different from the first material (FIG. 26C: el. 125; para. 91| second portion of sidewalls formed of silicon oxide dielectric), and a base of the trench is formed of third material that is different from the first material and the second material (FIG. 26C: el. 92; para. 54); and forming a backside via in the trench that includes a conducting material that is exposed at the backside of the substrate, extends through the substrate, and electrically couples with the source/drain structure (FIG. 27D: el. 130; para. 96). Chang fails to teach flowing a fluid into the trench that forms a uniform isolation layer on the first portion of the sidewalls of the trench and on the base of the trench, and does not form the isolation layer on the second portion of the sidewalls of the trench; removing a portion of the isolation layer covering the base of the trench to expose a portion of a source/drain structure.
In a similar field of endeavor, Kobayashi teaches treating sidewalls of a via trench by flowing a fluid into the trench that forms a uniform isolation layer on the first portion of the sidewalls of the trench and on the base of the trench (FIG. 4: el. 30, 22, 4; col. 2: line 31-38|silicon oxide isolation layer 30 formed on first portion 22 of sidewalls of the trench, which is a silicon portion of the sidewalls, and on a base 4 of the trench by an ashing process which is a process of flowing an oxygen containing fluid over the treated surface), and does not form the isolation layer on the second portion of the sidewalls of the trench (FIG. 4: el. (20, 24); col. 2: lines 13-18| isolation layer 30 is not formed on the second portion (20, 24) of the sidewalls of the trench, which is a silicon oxide layer); removing a portion of the isolation layer covering the base of the trench (FIG. 4, 6: el. 4; col. 2: lines 46-48| the portion of the oxide isolation layer formed on the base 4 is removed). The combination of Kobayashi and Chang teaches removing a portion of the isolation layer covering the base of the trench (Kobayashi - FIG. 4, 6: el. 4; col. 2: lines 31-38, 46-48| Kobayashi teaches an oxide isolation layer formed on the active region 4 at the base of the trench, and teaches removing the portion of the oxide isolation layer which is formed on the base before filling the trench with conductive material) to expose a portion of a source/drain structure (Chang – FIG. 26C: el. 92; para. 53-54| Chang teaches that the base of the trench is an active area consisting of a silicon-germanium source/drain structure 92). Kobayashi also teaches a benefit of forming an isolation layer on a first portion of the sidewalls of a trench is an increase in the diffusion barrier between silicon sidewalls of the trench and conductive material of a via formed in the trench while maximizing a width of the conductive fill of the trench (col. 3: lines 31-53).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Chang and Kobayashi, to enable using the formation of an isolation layer on a portion of a sidewall of a trench of Kobayashi in the method of Chang, for the benefit of increasing the resistance to diffusion of conductive fill materials into semiconductor sidewall materials while maintaining a maximized width and contact area of the conductive fill.
Re claim 16: The combination of Chang and Kobayashi teaches the method of claim 15, wherein the first material is silicon (Chang - FIG. 26C: el. 50; para. 16|first material of first portion of sidewalls formed of silicon substrate) and the isolation layer is formed of a dielectric material that includes an oxide of silicon (SiOx) or a nitride of silicon (SiNx) (Kobayashi - FIG. 4: el. 30; col. 2: line 31-38|isolation layer 30 formed of silicon oxide).
Re claim 18: The combination of Chang and Kobayashi teaches the method of claim 15, wherein the trench has a width in a range of between 5 and 30 nanometers (Chang - FIG. 26D: el. W8; para. 94| Chang specifically discloses that the width is between 20 and 70 nanometers, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”).
Re claim 21: Chang teaches a method, comprising: providing a semiconductor device comprising a source/drain feature on a substrate (FIG. 26C: el. 92, 50; para. 11-12); etching a trench (FIG. 26C: el. 128; para. 92) through a backside of the substrate (FIG. 26C: el. 50; para. 92) to a base of the source/drain feature (FIG. 26C: el. 128, 92), wherein a first portion of sidewalls of the trench is formed of first material (FIG. 26C: el. 50; para. 16|first portion of sidewalls formed of silicon substrate), a second portion of the sidewalls of the trench is formed of a second material that is different from the first material (FIG. 26C: el. 125; para. 91| second portion of sidewalls formed of silicon oxide dielectric), and a base of the trench is formed of third material that is different from the first material and the second material (FIG. 26C: el. 92; para. 54); and forming a backside via in the trench that includes a conducting material that is exposed at the backside of the substrate, extends through the substrate, and electrically couples with the source/drain feature (FIG. 27D: el. 130; para. 96). Chang fails to teach flowing a fluid into the trench that reacts with the first material of the first portion of the sidewalls of the trench to form an isolation layer, and does not react with the second material of the second portion, thereby forming the isolation layer on the first portion of the sidewalls.
In a similar field of endeavor, Kobayashi teaches treating sidewalls of a via trench by flowing a fluid into the trench that reacts with the first material of the first portion of the sidewalls of the trench to form an isolation layer (FIG. 4: el. 30, 22; col. 2: line 31-38|silicon oxide isolation layer 30 formed on first portion 22 of sidewalls of the trench, which is a silicon portion of the sidewalls, by an ashing process which reacts the silicon sidewall with an oxygen containing fluid flowed over the treated surface), and does not react with the second material of the second portion (FIG. 4: el. (20, 24); col. 2: lines 13-18| second portion (20, 24) of the sidewalls of the trench does not react with the oxygen containing fluid of the ashing process to form a silicon oxide isolation layer because the second portion is already a silicon oxide layer), thereby forming the isolation layer on the first portion of the sidewalls (FIG. 4: el. 30). Kobayashi also teaches a benefit of forming an isolation layer on a first portion of the sidewalls of a trench is an increase in the diffusion barrier between silicon sidewalls of the trench and conductive material of a via formed in the trench while maximizing a width of the conductive fill of the trench (col. 3: lines 31-53).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Chang and Kobayashi, to enable using the formation of an isolation layer on a portion of a sidewall of a trench of Kobayashi in the method of Chang, for the benefit of increasing the resistance to diffusion of conductive fill materials into semiconductor sidewall materials while maintaining a maximized width and contact area of the conductive fill.
Re claim 22: The combination of Chang and Kobayashi teaches the method of claim 21, wherein the first material is silicon (Chang - FIG. 26C: el. 50; para. 16|first material of first portion of sidewalls formed of silicon substrate) and the isolation layer is formed of a dielectric material that includes an oxide of silicon (SiOx) or a nitride of silicon (SiNx) (Kobayashi - FIG. 4: el. 30; col. 2: line 31-38|isolation layer 30 formed of silicon oxide).
Re claim 24: The combination of Chang and Kobayashi teaches the method of claim 21, wherein the trench has a width in a range of between 5 and 30 nanometers (Chang - FIG. 26D: el. W8; para. 94| Chang specifically discloses that the width is between 20 and 70 nanometers, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”).
Re claim 27: The combination of Chang and Kobayashi teaches the method of claim 21, wherein the fluid reacts with the third material of the base (Kobayashi - FIG. 4: el. 4; col. 2: line 31-38, Chang – FIG. 26C: el. 92; para. 53-54| Kobayashi teaches forming an isolation layer 30 on the active region 4 at the base of the trench, by an ashing process which is a process of flowing an oxygen containing fluid over the treated surface; Chang teaches the base of the trench is a third material formed of silicon-germanium, a material which is also well-known to oxidize to form an oxide layer in the presence of an oxidizing environment), wherein the method includes removing a portion of the isolation layer covering the base of the trench prior to forming the backside via (Kobayashi - FIG. 4, 6: el. 4; col. 2: 46-48| Kobayashi teaches removing the portion of the oxide isolation layer which is formed on the base of the trench before filling the trench with conductive material) to expose a portion of a source/drain structure (Chang – FIG. 26C: el. 92; para. 53-54| Chang teaches that the base of the trench is an active area consisting of a silicon-germanium source/drain structure 92).
Claims 17, 19, 23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Kobayashi as applied to claims 15 and 21 above, and further in view of Hsiung.
Re claim 17: The combination of Chang and Kobayashi teaches the method of claim 15, but is silent on the thickness of the isolation layer and therefore is silent on wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers.
In a similar field of endeavor, Hsiung teaches a method of forming a trench in a backside of a substrate to connect to a source/drain region of a gate-all-around transistor wherein an oxide isolation layer is formed on a first portion of the trench and not formed on a second portion of the trench, and teaches a functional range of thicknesses of the oxide isolation layer for use in this structure (FIG. 15A, 16A; para. 10, 48). Hsuing teaches wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers (para. 48| Hsuing specifically discloses that the thickness is from about 1 nm to about 3 nm, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Hsiung also teaches a benefit of providing an oxide isolation layer of this thickness is control of the sidewall etching profile with respect to the bottom of the trench and reduced leakage (para. 48, 125).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Chang and Kobayashi with the teachings of Hsiung, to enable using isolation layer thickness of Hsiung in the method of the combination of Chang and Kobayashi, for the benefit of simplifying manufacturing by using a known feature thickness for successfully integrating isolation layers into backside source/drain trenches of gate-all-around transistors, the benefit of reduced leakage, as well as the benefit of sidewall profile control.
Re claim 19: The combination of Chang and Kobayashi teaches the method of claim 15, but is silent on wherein forming the isolation layer includes flowing the fluid at a flow rate in a range of 1 and 20 sccm while providing a pressure in a range of 10 and 100 torr at a power in a range of 500 to 2000 watts for a time in a range of 60 to 360 seconds.
In a similar field of endeavor, Hsiung teaches a method of forming a trench in a backside of a substrate to connect to a source/drain region of a gate-all-around transistor wherein an oxide isolation layer is formed on a first portion of the trench and not formed on a second portion of the trench, and teaches process parameters for the formation of the oxide isolation layer (FIG. 15A, 16A; para. 10, 46-48). Hsuing teaches a power in a range of 500 to 2000 watts (para. 48| Hsiung specifically discloses that the power is 50 to 1000 watts, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Hsiung fails to directly disclose the range of the flow rate, pressure, and time, but teaches processing parameters as result-effective variables for controlling the thickness and uniformity of the isolation layer (para. 46-48). Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the well-known result-effective variables of flow rate, pressure, and time, to achieve the claimed range, as a matter of routine optimization for the benefit of forming an isolation layer with a desired thickness and uniformity.
Re claim 23: The combination of Chang and Kobayashi teaches the method of claim 21, but is silent on the thickness of the isolation layer and therefore is silent on wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers.
In a similar field of endeavor, Hsiung teaches a method of forming a trench in a backside of a substrate to connect to a source/drain region of a gate-all-around transistor wherein an oxide isolation layer is formed on a first portion of the trench and not formed on a second portion of the trench, and teaches a functional range of thicknesses of the oxide isolation layer for use in this structure (FIG. 15A, 16A; para. 10, 48). Hsuing teaches wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers (para. 48| Hsuing specifically discloses that the thickness is from about 1 nm to about 3 nm, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Hsiung also teaches a benefit of providing an oxide isolation layer of this thickness is control of the sidewall etching profile with respect to the bottom of the trench and reduced leakage (para. 48, 125).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Chang and Kobayashi with the teachings of Hsiung, to enable using isolation layer thickness of Hsiung in the method of the combination of Chang and Kobayashi, for the benefit of simplifying manufacturing by using a known feature thickness for successfully integrating isolation layers into backside source/drain trenches of gate-all-around transistors, the benefit of reduced leakage, as well as the benefit of sidewall profile control.
Re claim 25: The combination of Chang and Kobayashi teaches the method of claim 21, but is silent on wherein forming the isolation layer includes flowing the fluid at a flow rate in a range of 1 and 20 sccm while providing a pressure in a range of 10 and 100 torr at a power in a range of 500 to 2000 watts for a time in a range of 60 to 360 seconds.
In a similar field of endeavor, Hsiung teaches a method of forming a trench in a backside of a substrate to connect to a source/drain region of a gate-all-around transistor wherein an oxide isolation layer is formed on a first portion of the trench and not formed on a second portion of the trench, and teaches process parameters for the formation of the oxide isolation layer (FIG. 15A, 16A; para. 10, 46-48). Hsuing teaches a power in a range of 500 to 2000 watts (para. 48| Hsiung specifically discloses that the power is 50 to 1000 watts, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Hsiung fails to directly disclose the range of the flow rate, pressure, and time, but teaches processing parameters as result-effective variables for controlling the thickness and uniformity of the isolation layer (para. 46-48). Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the well-known result-effective variables of flow rate, pressure, and time, to achieve the claimed range, as a matter of routine optimization for the benefit of forming an isolation layer with a desired thickness and uniformity.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Kobayashi as applied to claim 21 above, and further in view of Guha.
Re claim 28: The combination of Chang and Kobayashi fails to teach the method of claim 21, wherein the fluid does not react with the third material of the base.
In a similar field of endeavor, Guha teaches forming a gate-all-around transistor (FIG. 10A; para. abstract) with a silicon oxide source/drain insulating layer (FIG. 10A: el. 351; para. 61-62) between the source/drain and the semiconductor substrate (FIG. 10A: el. 351, 360, 300). Guha teaches a benefit of the insulating layer between the source/drain and the semiconductor substrate is a reduction in leakage currents in the area below the gates and source/drain (para. 34).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Chang and Kobayashi with the teachings of Guha, to enable using the insulating layer between a source/drain region and a substrate of Guha in the method of the combination of Chang and Kobayashi, for the benefit of reduced leakage currents in the area of the semiconductor substrate adjacent to the gates and source/drain regions.
The combination of Chang, Kobayashi, and Guha teaches flowing a fluid into the trench that reacts with the first material of the first portion of the sidewalls of the trench to form an isolation layer (Kobayashi - col. 2: lines 31-38| silicon oxide isolation layer 30 formed on the first portion 22 of the sidewalls of the trench by an ashing process which reacts the silicon sidewall 22 with an oxygen containing fluid flowed over the treated surface), and does not react with the second material of the second portion (Kobayashi - FIG. 4: el. (20, 24); col. 2: lines 13-18| second portion (20, 24) of the sidewalls of the trench does not react with the oxygen containing fluid of the ashing process to form a silicon oxide isolation layer because the second portion is already a silicon oxide layer), thereby forming the isolation layer on the first portion of the sidewalls (Kobayashi - FIG. 4: el. 30), wherein the fluid does not react with the third material of the base (Chang – FIG. 26C: el. 128, 50, 92, Guha – Fig. 10A: el. 351, 360, 300| Chang teaches forming a trench in the backside of the substrate 50 to a depth of a material 92 of the source/drain area, which is adjacent to the substrate 50; Guha teaches a silicon oxide source/drain insulating layer 351 as the material of the source/drain area adjacent to the substrate 300; the combination teaches wherein the base of the trench is formed of the silicon oxide source/drain insulating layer, which is the third material; the combination also teaches wherein the fluid does not react with the third material of the base because the base of the trench is already formed of silicon oxide).
Allowable Subject Matter
Claims 14, 20, and 26 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 14: The closest prior art, Chang'155, Kobayashi’863, Guha’087, either alone or in combination fails to disclose or suggest, “forming a second masking layer on the first masking layer, wherein forming the trench includes performing a photolithography and etching process to form the trench through the first masking layer and the second masking layer; and removing the second masking layer after forming the backside via by a chemical mechanical polishing process,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 20: The closest prior art, Chang'155, Kobayashi’863, Guha’087, either alone or in combination fails to disclose or suggest, “forming a second masking layer on the first masking layer, wherein forming the trench includes performing a photolithography and etching process to form the trench through the first masking layer and the second masking layer; and removing the second masking layer after forming the backside via by a chemical mechanical polishing process,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 26: The closest prior art, Chang'155, Kobayashi’863, Guha’087, either alone or in combination fails to disclose or suggest, “forming a second masking layer on the first masking layer, wherein forming the trench includes performing a photolithography and etching process to form the trench through the first masking layer and the second masking layer; and removing the second masking layer after forming the backside via by a chemical mechanical polishing process,” in combination with the additionally claimed features, as claimed by the applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art made of record and not relied upon teaches forming trenches to a source/drain region from a backside of a substrate.
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/D.G./ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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