DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10 and 13-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Reznicek et al. (U.S. Patent No. 11,315,938).
Regarding to claim 10, Reznicek teaches a method for forming an isolator in a complementary field effect transistor (CFET), comprising:
fabricating a plurality of CFET devices, each CFET device including a first metal-oxide- semiconductor (MOS) device and a second MOS device, wherein the first MOS device and the second MOS device are complementary devices (Fig. 4, column 4, lines 52-57);
removing a filler material between the first MOS device and the second MOS device of a first CFET device (Fig. 5, column 9, line 31, removing filler material 14 between the first MOS device and the second MOS device of a first CFET device), wherein the CFET device includes a first sidewall between the first CFET device and a second CFET device, and a second sidewall between the first CFET device and a third CFET device (please see the attached figure with annotation); and
depositing selectively a dielectric material between the first CFET device and the second CFET device only on a predefined region, to fill a void between the first MOS device and the second MOS device of the first CFET device (Fig. 6, column 9, lines 40-41, depositing selectively dielectric material 54 between the first CFET device and the second CFET device only on predefined region, the region where material 14 was removed, to fill a void between the first MOS device and the second MOS device of the first CFET device).
Regarding to claim 13, Reznicek teaches the selective deposition is determined based on any one of: a CFET architecture, a size of the void, an area of the void, a volume of the void, a dimension of the void, a type of material used as NPDI filler, and any combination thereof (Fig. 6, based on size of the void, where material 14 has been removed).
Regarding to claim 14, Reznicek teaches etching away the filler material (Fig. 5, column 9, lines 35-36).
PNG
media_image1.png
862
1393
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. Patent No. 11,177,258) in view of Nelson et al. (U.S. Patent No. 9,721,828).
Regarding to claim 1, Xie teaches a method for forming an isolator in a complementary field effect transistor (CFET), comprising:
fabricating a plurality of CFET devices, each CFET device including a first metal oxide- semiconductor (MOS) device and a second MOS device, wherein the first MOS device and the second MOS device are complementary devices (Fig. 6; column 5, lines 15-20);
removing a filler material between the first MOS device and the second MOS device of a first CFET device (Fig. 14, column 11, lines 5-8);
depositing a dielectric material between the first CFET device and a second CFET device to fill a void between the first MOS device and the second MOS device of the first CFET device (Fig. 16, column 11, lines 22-26).
Xie does not disclose etching the dielectric material, repeating the depositing and etching steps to fill the void between the first MOS device and the second MOS device of the first CFET device, and performing a final etching to remove the dielectric material between the first CFET and the second CFET.
Nelson discloses repeating the depositing and etching steps to fill a void (column 5, lines 7-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Xie in view of Nelson to etch the dielectric material, repeat the depositing and etching steps to fill the void between the first MOS device and the second MOS device of the first CFET device, and perform a final etching to remove the dielectric material between the first CFET and the second CFET, on order to ensure no material left between the FETs before next material deposition steps are performed.
Regarding to claim 4, Xie teaches removing the filler further comprises etching away the filler material (Fig. 14).
Allowable Subject Matter
Claims 5-9 are allowed.
Claims 2-3 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 2, the prior art fails to anticipate or render obvious the claimed limitations including “determining a number of times to repeat the depositing and etching steps” in combination with the limitations recited in claim 1.
Regarding to claim 5, the prior art fails to anticipate or render obvious the claimed limitations including “poisoning the first sidewall and the second sidewall to inhibit dielectric adhesion” in combination with the rest of limitations recited in claim 5.
Claims 6-9 are allowable for the same reasons with claim 5 which they are dependent from.
Regarding to claim 11, the prior art fails to anticipate or render obvious the claimed limitations including “poisoning the first sidewall and the second sidewall to inhibit dielectric adhesion” in combination with the rest of limitations recited in claim 10.
Pertinent Art
For the benefits of the Applicant, US-12471364-B2 US-10347741-B1, US-10510865-B2, US-20240429277-A1, US-20240072115-A1, US-20250125213-A1, and US-20190172723-A1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including “removing a filler material between the first MOS device and the second MOS device of a first CFET device, wherein the CFET device includes a first sidewall between the first CFET device and a second CFET device, and a second sidewall between the first CFET device and a third CFET device, poisoning the first sidewall and the second sidewall to inhibit dielectric adhesion.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VU A VU/Primary Examiner, Art Unit 2897