DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 20220149160 A1 Ishibashi et al hereafter “Ishibashi”.
Claim 1 Ishibashi teaches A SiC epitaxial wafer, comprising: a SiC wafer (10 fig. 2); and
a SiC epitaxial layer (20 fig. 2) on one surface of the SiC wafer,
wherein the SiC epitaxial layer has a buffer layer (21 fig. 2) and a drift layer (22 fig. 2),
wherein the buffer layer is disposed between the drift layer and the SiC wafer [sufficiently illustrated fig. 2], and has a higher impurity concentration than the drift layer [sufficiently disclosed paragraph 0048 “a SiC epitaxial layer 20 includes a high concentration layer 21, which is a buffer layer, and a drift layer 22 that is provided on the buffer layer and has an average value of the doping concentration lower than an average value of the doping concentration of the buffer layer”],
basal plane dislocations, wherein there is a number of first basal plane dislocations in a thickness direction from an interface (10a fig. 2) between the SiC wafer and the SiC epitaxial layer [sufficiently disclosed paragraph 0058 “the basal dislocations of the SiC single crystal substrate at an interface between the epitaxial layer and the SiC single crystal substrate, +carriers (holes) and −carriers (electrons) are recombined, and the basal plane dislocations expand to the epitaxial layer”].
the SiC epitaxial wafer has a diameter of 149 mm or more [disclosed with sufficient specificity paragraph 0051 “150 mm or more” see MPEP 2131.03 II.].
Ishibashi does not explicitly teach the number of the first basal plane dislocations having a height of 1µm or less in a thickness direction from an interface between the SiC wafer and the SiC epitaxial layer is 20 or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as a part of routine optimization to reduce and/or minimize the size and number of basal plane dislocations such that “the number of the first basal plane dislocations having a height of 1µm or less in a thickness direction from an interface between the SiC wafer and the SiC epitaxial layer is 20 or less” to reduce fatal defects and/or reduce resistance stacking in faults and/or improve reliability and/or lower forward deterioration [Disclosed Paragraph 0007 Ishibashi] [See MPEP 2144.05 II].
Claim 2 Ishibashi teaches A SiC epitaxial wafer, comprising:
a SiC wafer (10 fig. 2); and
a SiC epitaxial layer (20 fig. 2) on one surface of the SiC wafer,
wherein the SiC epitaxial layer has a buffer layer (21 fig. 2) and a drift layer (22 fig. 2),
wherein the buffer layer is disposed between the drift layer and the SiC wafer [sufficiently illustrated fig. 2], and has a higher impurity concentration than the drift layer [sufficiently disclosed Paragraph 0048 “a SiC epitaxial layer 20 includes a high concentration layer 21, which is a buffer layer, and a drift layer 22 that is provided on the buffer layer and has an average value of the doping concentration lower than an average value of the doping concentration of the buffer layer”],
basal plane dislocations, wherein there is a number of first basal plane dislocations in a thickness direction from an interface (10a fig. 2) between the SiC wafer and the SiC epitaxial layer [sufficiently disclosed paragraph 0058 “the basal dislocations of the SiC single crystal substrate at an interface between the epitaxial layer and the SiC single crystal substrate, +carriers (holes) and −carriers (electrons) are recombined, and the basal plane dislocations expand to the epitaxial layer”].
the SiC epitaxial wafer has a diameter of 199 mm or more [disclosed with sufficient specificity paragraph 0051 “150 mm or more” see MPEP 2131.03 II.].
Ishibashi does not explicitly teach the number of the first basal plane dislocations having a height of 1lxm or less in a thickness direction from an interface between the SiC wafer and the SiC epitaxial layer is 20 or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as a part of routine optimization to reduce the size and number of basal plane dislocations such that “the number of the first basal plane dislocations having a height of 1lxm or less in a thickness direction from an interface between the SiC wafer and the SiC epitaxial layer is 35 or less” to reduce fatal defects and/or reduce resistance stacking in faults and/or improve reliability and/or lower forward deterioration [Disclosed Paragraph 0007 Ishibashi] [See MPEP 2144.05 II]
Claim 5 Ishibashi teaches as shown above the SiC epitaxial wafer according to claim 1 wherein the buffer layer has an impurity concentration of 5.0x1017/cm3 or more [sufficiently disclosed Paragraph 0082 “5x1017/cm3 or more”].
Claim 6 Ishibashi teaches as shown above the SiC epitaxial wafer according to claim 2 wherein the buffer layer has an impurity concentration of 5.0x1017/cm3or more [sufficiently disclosed Paragraph 0082 “5x1017/cm3 or more”].
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ishibashi as applied to the claims above, and further in view of US 20220170179 A1 Honke et al hereafter “Honke”.
Claim 3 modified Ishibashi teaches The SiC epitaxial wafer according to claim 1,
Ishibashi does not explicitly teach when a measurement region excluding an exclusion region within 5 mm from the outer circumference of the SiC epitaxial layer is divided into 5 mm squares, the number of first basal plane dislocations is less than 3 in 98% or more of the entire
divided area
Honke teaches a measurement region (comprising at least a portion of 50 and/or 45 fig. 3) excluding an exclusion region ( comprising at least 51a, 51b, 51c, 51d and/or 41 fig. 3) within 5 mm from the outer circumference of the SiC layer [sufficiently illustrated fig. 3] is divided into 5 mm squares [sufficiently illustrated fig. 3] .
It would have been obvious to one of ordinary skill in the art to combine the device Ishibashi teaches with the device Honke teaches such that “a measurement region excluding an exclusion region within 5 mm from the outer circumference of the SiC epitaxial layer is divided into 5 mm squares” for the benefit of “An average value of LTVs of a plurality of first square regions of a plurality of square regions is less than or equal to 0.75 μm” and/or “to provide a largest number of square regions” [Honke Paragraph 0004] and/or combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] wherein they both serve the purpose of SiC wafers and/or chips for semiconductor device manufacturing.
In view of the modification made above the limitation “the number of first basal plane dislocations is less than 3 in 98% or more of the entire divided area” is necessarily met as part of the routine optimization of the number of basal plane dislocation as shown in claim 1 for the same reasons as shown in claim 1.
Claim 4 Ishibashi teaches as shown above the SiC epitaxial wafer according to claim 2.
Ishibashi does not explicitly teach when a measurement region excluding an exclusion region within 5 mm from the outer circumference of the SiC epitaxial layer is divided into 5 mm squares, the number of first basal plane dislocations is less than 3 in 98% or more of the entire
divided area
Honke teaches a measurement region (comprising at least a portion of 50 and/or 45 fig. 3) excluding an exclusion region ( comprising at least 51a, 51b, 51c, 51d and/or 41 fig. 3) within 5 mm from the outer circumference of the SiC layer [sufficiently illustrated fig. 3] is divided into 5 mm squares [sufficiently illustrated fig. 3] .
It would have been obvious to one of ordinary skill in the art to combine the device Ishibashi teaches with the device Honke teaches such that “a measurement region excluding an exclusion region within 5 mm from the outer circumference of the SiC epitaxial layer is divided into 5 mm squares” for the benefit of “An average value of LTVs of a plurality of first square regions of a plurality of square regions is less than or equal to 0.75 μm” and/or “to provide a largest number of square regions” [Honke Paragraph 0004] and/or combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] wherein they both serve the purpose of SiC wafers and/or chips for semiconductor device manufacturing.
In view of the modification made above the limitation “the number of first basal plane dislocations is less than 3 in 98% or more of the entire divided area” is necessarily met as part of the routine optimization of the number of basal plane dislocation as shown in claim 1 for the same reasons as shown in claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WCT/Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893