Prosecution Insights
Last updated: August 18, 2026
Application No. 18/394,999

Carrier-Assisted Method for Parting Crystalline Material Along Laser Damage Region

Final Rejection §103§112
Filed
Dec 22, 2023
Priority
Dec 29, 2018 — provisional 62/786,335 +3 more
Examiner
BRATLAND JR, KENNETH A
Art Unit
1714
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Wolfspeed Inc.
OA Round
5 (Final)
56%
Grant Probability
Moderate
6-7
OA Rounds
6m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 56% of resolved cases
56%
Career Allowance Rate
495 granted / 881 resolved
-8.8% vs TC avg
Strong +16% interview lift
Without
With
+16.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
48 currently pending
Career history
930
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
52.0%
+12.0% vs TC avg
§102
14.6%
-25.4% vs TC avg
§112
23.6%
-16.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 881 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The 35 U.S.C. 112(a) rejection of claims 110-113, 115-120, 127, 129, and 138-139 is withdrawn in view of applicants’ arguments and claim amendment. The 35 U.S.C. 112(b) rejection of claim 138 is withdrawn in view of applicants’ arguments and claim amendment. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 110-112, 116, 119, 129, and 138 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Appl. Publ. No. 2014/0197419 to Henley, et al. (hereinafter “Henley”) in view of U.S. Patent Appl. Publ. No. 2014/0038392 to Yonehara, et al. (“Yonehara”) and further in view of U.S. Patent Appl. Publ. No. 2014/0087504 to Li, et al. (“Li”). Regarding claim 110, Henley teaches a semiconductor processing method (see, e.g., the Abstract, Figs. 1-36, and entire reference), comprising: temporarily bonding a carrier to a first surface of a wafer of crystalline material with an intervening adhesive material (see, e.g., Figs. 24-31 and ¶¶[0186]-[0215] which teach that a rigid workpiece (2501) is bonded to a top surface (2403) of a crystalline substrate such as a GaN wafer (2400) with ¶[0197] specifically teaching that the bonding may be achieved using an adhesive material), wherein the adhesive material is provided directly over a first surface of the wafer of crystalline material (see, e.g., Figs. 24-31 and ¶¶[0186]-[0215] which teach that the GaN wafer (2400) includes material region to be removed (2401) above a subsurface damage region (2411) with ¶[0197] specifically teaching that the bonding may be achieved using an adhesive material which necessarily involves applying the adhesive material directly over a top surface (2403) of the material region (2401) of the GaN wafer (2400)), and fracturing the wafer of crystalline material along or proximate to a damage region to yield a bonded assembly comprising the carrier, the adhesive material, and a portion of the crystalline substrate (see, e.g., Figs. 24-31 and ¶¶[0186]-[0215] which teach that a controlled cleaving action is initiated along a subsurface damage region (2411) to remove the crystalline substrate (2400) and produce a bonded assembly comprising the rigid workpiece (2501), adhesive layer (2605), and the epitaxial layer (2401) removed from the crystalline substrate (2400)). Henley does not teach that the wafer of crystalline material has a damage region at a depth relative to the first surface in the substrate that is formed independent of the bonding step. However, in Figs. 6-7 and ¶¶[0070]-[0076] as well as elsewhere throughout the entire reference Yonehara teaches an analogous method of transferring a device layer present on a donor wafer to a handle substrate. As shown in Figs. 6A-B the device layer is first bonded to the handle substrate and this is then followed by forming a damage region by irradiating a laser from a back side of the donor wafer in order to produce a splitting layer which facilitates release of the device layer. In this manner it is possible to reuse the host wafer for multiple device layer formation and release cycles. Moreover, by irradiating the laser from the back side of the donor wafer the potential for damaging the device layer by having the laser pass therethrough is minimized. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Yonehara and would recognize that the damage region utuilized in the method of Henley may be formed after being bonded to the carrier by irradiation with a laser from a back side of the wafer of crystalline material in order to promote ease of detachment of the wafer of crystalline material from the carrier. Henley and Yonehara do not teach that one or more epitaxial layers are on a first surface of the wafer of crystalline material. However, in Figs. 1-5 and ¶¶[0032]-[0075] as well as elsewhere throughout the entire reference Li teaches an analogous method of generating a single crystal semiconductor layer in which OLED driving circuitry (12), logic/memory devices (14), and other functions (15) provided on the surface of a semiconductor substrate (10) are separated from the bulk of the substrate (10) by the spalling technique. It is noted that the driving circuitry (12), logic/memory devices (14), and other functions (15) must necessarily be comprised of or, alternatively, would be reasonably expected to be comprised of one or more epitaxial layers grown on the substrate (10) as part of a device fabrication process. Separation of the device layer in the method of Li is achieved by initially forming a stressor layer (20) and handle substrate (22) on the surface of the semiconductor substrate (10) and then cooling to temperatures below 20 °C such that the portion (10B) of the substrate (10) that contains the circuitry (12) and devices (14) is separated from the portion (10A) that does not. Portion (10A) may then be subject to additional device processing steps. Thus, person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Li and would readily recognize that the crystal material processing method of Henley may also be used to separate a top layer of a device wafer which includes electronic devices and/or driving circuitry formed by one or more epitaxial deposition processes from the bulk of the substrate with the motivation for doing so being to utilize a simpler separation process which produces a well-defined cleavage plane and requires fewer processing steps. Regarding claim 111, Henley does not teach removing the carrier from the bonded assembly. However, in Figs. 4-5 and ¶¶[0072]-[0075] Li teaches that after the desired processing is performed on the spalled layer (10B), the handle substrate (22), the stressor layer (20), and the protection layer (18) are removed such that a free-standing structure is provided. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to remove the rigid workpiece (2501) and any remaining adhesive layer after the desired processing of the epitaxial layer (2401) has been performed in order to produce a free-standing structure which can be processed into individual devices. Regarding claim 112, Henley does not teach removing the adhesive material from the bonded assembly. However, in Figs. 4-5 and ¶¶[0072]-[0075] Li teaches that after the desired processing is performed on the spalled layer (10B), the handle substrate (22), the stressor layer (20), and the protection layer (18) are removed such that a free-standing structure is provided. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would be motivated to remove the rigid workpiece (2501) and any remaining adhesive layer after the desired processing of the epitaxial layer (2401) has been performed in order to produce a free-standing structure which can be processed into individual devices. Regarding claim 116, Henley teaches that prior to temporarily providing the adhesive material on the wafer of crystalline material, the method comprises forming one or more conductive contacts on the one or more epitaxial layers (see, e.g., Figs. 24-31 and ¶¶[0186]-[0215] which teach forming a layer (2402) of one or more metal films on the epitaxial layer (2401) prior to providing an adhesive material; alternatively, in Fig. 1 and ¶[0032] Li teaches that the surface of the crystalline semiconductor substrate (10) includes driving circuitry (12) and logic and memory devices (14) which would necessarily entail forming one or more conductive contacts on a surface thereof). Regarding claim 119, Henley teaches that the wafer of crystalline material comprises silicon carbide (see, e.g., ¶[0013], ¶[0097], and ¶[0233] which teach that the crystalline substrate (2400) may be a SiC substrate which necessarily would be in the form of a wafer). Regarding claim 129, Henley teaches that fracturing the wafer of crystalline material along or proximate to the damage region to yield a bonded assembly comprises one or more of: application of ultrasonic energy to at least one of the carrier or the wafer of crystalline material; or applying a mechanical force to the carrier (see, e.g., Figs. 17-23 and ¶¶[0160]-[0170] which teach that selective energy placement provides a controlled cleaving action of the material region (12) and that the energy source may be mechanical in nature, derived from rotational, translational, compressional, and expansional forces (1701) and (1707) , and applied in the vicinity of the subsurface damaged region in order to initiate and propagate a cleaving action; thus, a person of ordinary skill in the art would look to the teachings of Henley and would be motivated to apply a mechanical force to impart a bending moment to the rigid carriers in order to promote a more efficient cleaving action along the subsurface damaged region). Regarding claim 138, Henley and Li do not teach that the damage region is formed subsequent to temporarily bonding the carrier to the first surface of the wafer of crystalline material. However, in Figs. 6-7 and ¶¶[0070]-[0076] as well as elsewhere throughout the entire reference Yonehara teaches an analogous method of transferring a device layer present on a donor wafer to a handle substrate. As shown in Figs. 6A-B the device layer is first bonded to the handle substrate and this is then followed by forming a damage region by irradiating a laser from a back side of the donor wafer in order to produce a splitting layer which facilitates release of the device layer. In this manner it is possible to reuse the host wafer for multiple device layer formation and release cycles. Moreover, by irradiating the laser from the back side of the donor wafer the potential for damaging the device layer by having the laser pass therethrough is minimized. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Yonehara and would recognize that the damage region utilized in the method of Henley may be formed after being bonded to the carrier by irradiation with a laser from a back side of the wafer of crystalline material in order to promote ease of detachment of the wafer of crystalline material from the carrier. Claims 113 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henley in view of Yonehara and further in view of Li and still further in view of U.S. Patent Appl. Publ. No. 2015/0171045 to Berger, et al. (“Berger”). Regarding claim 113, Henry, Yonehara, and Li do not teach that fracturing the wafer of crystalline material along or proximate to the damage region comprises: temporarily bonding a second carrier to a second surface of the wafer of crystalline material, the second surface being opposite the first surface; and fracturing the wafer of crystalline material along or proximate to the damage region to yield a second bonded assembly comprising the second carrier and a second portion of the wafer of crystalline material. However, in Figs. 1-5 and ¶¶[0021]-[0150] Berger teaches an embodiment of a method for delaminating a thin layer from a semiconductor (10) such as SiC which includes bonding a first rigid carrier (20) to a first surface of the semiconductor (10) by means of a bonding layer (15), forming a delamination layer (13) within the semiconductor (10) by ion implantation, and bonding a second rigid carrier (22) to a second, opposite side of the semiconductor (10) by means of a second bonding layer (16). In ¶¶[0122]-[0130] Berger specifically teaches that a thermal treatment is utilized to cause mechanical tensions which result in separation of a thin layer (11) along the delamination layer (13). The separated compound structure (32) can then be reused in order to produce additional thin layers (11) of said semiconductor (10). Thus, in view of the teachings of Berger a person of ordinary skill in the art prior to the effective filing date of the invention would readily recognize that separation of the material region (2401) along the subsurface damage region (2411) in Figs. 24-27 of Henley may be further facilitated by bonding an additional rigid carrier to a second surface of the substrate (2400) and then performing a thermal treatment which causes mechanical tensions that facilitates separation along the subsurface damage region (2411). Claims 115, 117-118, and 139 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henley in view of Yonehara and further in view of Li and still further in view of U.S. Patent Appl. Publ. No. 2016/0193691 to Hirata, et al. (“Hirata”). Regarding claim 115, Henley and Li do not teach that the damage region is a laser damage region. However, as noted supra with respect to the rejection of claim 110, in Figs. 6-7 and ¶¶[0070]-[0076] as well as elsewhere throughout the entire reference Yonehara teaches an analogous method of transferring a device layer present on a donor wafer to a handle substrate. As shown in Figs. 6A-B the device layer is first bonded to the handle substrate and this is then followed by forming a damage region by irradiating a laser from a back side of the donor wafer in order to produce a splitting layer which facilitates release of the device layer. The use of a laser to produce a damage region is also taught by Hirata in at least Figs. 1-8 and ¶¶[0027]-[0060] which teach an embodiment of a system and method for cleaving a wafer from a substrate by using a focused laser beam to initiate a cleavage plane. In Figs. 5-8 and ¶¶[0034]-[0054] Hirata specifically teaches that a cleavage plane may be formed in a crystalline ingot (11) by scanning a laser beam with a focal point at a depth (D1) across the surface of the ingot (11) in a predetermined raster pattern such that a modified layer (23) with cracks (25) propagating therefrom is formed at a depth (D1) corresponding to the thickness of the wafer to be produced. This wafer may then be removed from the ingot (11) by initiating fracture along the modified layer (23). Thus, in view of the teachings of Yonehara and Hirata a person of ordinary skill in the art prior to the effective filing date of the invention would readily recognize that the subsurface damage region (2411) produced in the method of Henley may be produced using a laser beam since this would involve nothing more than the use of an alternative and known technique for producing a cleavage plane according to its intended use. The specific motivation for using a laser instead of ion implantation to produce a subsurface damage region would be, for example, to benefit from the use of a technique which is readily available and does not require a consumable product such as a source of implanted ions. Regarding claim 117, Henley and Li do not teach that the method comprises: inducing the damage region in the wafer of crystalline material with one or more lasers. However, as noted supra with respect to the rejection of claims 110 and 115, in Figs. 6-7 and ¶¶[0070]-[0076] as well as elsewhere throughout the entire reference Yonehara teaches an analogous method of transferring a device layer present on a donor wafer to a handle substrate. As shown in Figs. 6A-B the device layer is first bonded to the handle substrate and this is then followed by forming a damage region by irradiating a laser from a back side of the donor wafer in order to produce a splitting layer which facilitates release of the device layer. The use of a laser to produce a damage region is also taught by Hirata in Figs. 1-8 and ¶¶[0027]-[0060] Hirata teaches an embodiment of a system and method for cleaving a wafer from a substrate by using a focused laser beam to initiate a cleavage plane. In Figs. 5-8 and ¶¶[0034]-[0054] Hirata specifically teaches that a cleavage plane may be formed in a crystalline ingot (11) by scanning a laser beam with a focal point at a depth (D1) across the surface of the ingot (11) in a predetermined raster pattern such that a modified layer (23) with cracks (25) propagating therefrom is formed at a depth (D1) corresponding to the thickness of the wafer to be produced. This wafer may then be removed from the ingot (11) by initiating fracture along the modified layer (23). Thus, in view of the teachings of Yonehara and Hirata a person of ordinary skill in the art prior to the effective filing date of the invention would readily recognize that the subsurface damage region (2411) produced in the method of Henley may be produced using a laser beam since this would involve nothing more than the use of an alternative and known technique for producing a cleavage plane according to its intended use. The specific motivation for using a laser instead of ion implantation to produce a subsurface damage region would be, for example, to benefit from the use of a technique which is readily available and does not require a consumable product such as a source of implanted ions. Regarding claim 118, Henley teaches removing a rounded edge of the wafer of crystalline material prior to inducing the damage region in the wafer of crystalline material with one or more lasers (see, e.g., ¶¶[0187]-[0190] which teach that the bonding surfaces may be treated in order to promote good bondability by, for example, a clean/etch chemical bath that removes asperities and surface contaminants; moreover, the clean/etch chemical bath will necessarily remove a portion of the rounded edge of the substrate as claimed). Regarding claim 139, Henley, Li, and Hirata do not teach that inducing the damage region in the wafer of crystalline material with the one or more lasers comprises applying the one or more lasers through a second surface of the wafer of crystalline material, the second surface being opposite the first surface of the wafer of crystalline material. However, as noted supra with respect to the rejection of claims 110 and 117, in Figs. 6-7 and ¶¶[0070]-[0076] as well as elsewhere throughout the entire reference Yonehara teaches an analogous method of transferring a device layer present on a donor wafer to a handle substrate. As shown in Figs. 6A-B the device layer is first bonded to the handle substrate and this is then followed by forming a damage region by irradiating a laser from a back side of the donor wafer in order to produce a splitting layer which facilitates release of the device layer. In this manner it is possible to reuse the host wafer for multiple device layer formation and release cycles. Moreover, by irradiating the laser from the back side of the donor wafer the potential for damaging the device layer by having the laser pass therethrough is minimized. Thus, a person of ordinary skill in the art prior to the effective filing date of the invention would look to the teachings of Yonehara and would recognize that the damage region formed in the method of Henley may be reinforced and/or supplemented after being bonded to the carrier by irradiation with a laser from a back side of the wafer of crystalline material in order to promote ease of detachment of the wafer of crystalline material from the carrier. Claims 120 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henley in view of Yonehara and further in view of Li and still further in view of a Brewer Science Product literature for BrewerBOND 220 dated August 27, 2014 (hereinafter “Brewer”). Regarding claim 120, Henley, Yonehara, and Li do not teach that the adhesive material comprises a thermoplastic material. However, in ¶[0197] Henley teaches that wafer bonding may be achieved using an adhesive material and then Brewer teaches an embodiment of a thermoplastic wafer bonding adhesive known as BrewerBOND 220 which is suitable for use as a temporary wafer bonding material during compound semiconductor wafer processes in the 200 to 240 °C range. Thus, in view of the teachings of Brewer an ordinary artisan would be motivated to utilize a thermoplastic material such as BrewerBOND 220 as an adhesive material since this is a known thermoplastic material that would function according to its intended use in the method of Henley. Claim 127 is/are rejected under 35 U.S.C. 103 as being unpatentable over Henley in view of Yonehara and further in view of Li and still further in view of U.S. Patent Appl. Publ. No. 2012/0000415 to D’Evelyn, et al. (“D’Evelyn”). Regarding claim 127, Henley, Yonehara, and Li do not teach that the carrier has a thickness of 800 mm or more. However, in ¶¶[0044]-[0047] Henley teaches that the handle substrate is designed as a rigid carrier having a thickness sufficient to support and facilitate handling of the thin crystalline layer that is cleaved from the crystalline substrate. In this case the thickness of the handle substrate (i.e., the rigid carrier) is directly proportional to its rigidity and is therefore considered to be a result-effective variable, i.e., a variable which achieves a recognized result. See, e.g., In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977). See also MPEP 2144.05(II)(B). In ¶¶[0046]-[0047] Henley specifically teaches that the handle substrate may be any monocrystal material and may be further supported by a backing substrate in the form of a Si wafer or quartz handle substrate. Then in Figs. 1d-1g and ¶¶[0031]-[0041] D’Evelyn teaches an analogous method of transferring an epitaxial layer (105) from a single crystal (101) to a handle substrate (117). In ¶[0018] D’Evelyn specifically teaches that the nitride crystal used as the single crystal (101) in Figs. 1d-1g may have a thickness of between 100 mm to 100 mm. Thus, in view of the combined teachings of Henley and D’Evelyn an ordinary artisan would recognize the desirability of utilizing a handle substrate having a thickness sufficient to impart the desired rigidity. Furthermore, it would have been within the capabilities of an ordinary artisan to utilize routine experimentation to determine the optimal handle substrate thickness necessary to provide the desired level of support and rigidity to the fractured crystalline material. Since the teachings of D’Evelyn show that the single crystal may have a thickness of 100 mm to 100 mm an ordinary artisan would reasonably expect to utilize a rigid carrier having an analogous thickness which includes the claimed range of greater than 800 microns. Response to Arguments Applicants’ arguments filed June 26, 2026, have been fully considered, but they are not persuasive and are moot in view of the new grounds of rejection set forth in this Office Action. Applicants argue that Li does not teach or suggest that an epitaxial layer is present on the surface of the substrate because Li allegedly discloses the genus of “deposition,” but does not teach the species of forming an epitaxial layer and because the devices are formed within rather than on the substrate such as within a SOI wafer. See applicants’ 6/26/2026 reply, pp. 6-7. Applicants’ argument is noted, but is unpersuasive. Initially the Examiner notes that applicants’ analogy is misplaced as the process of “deposition” is not a genus. Rather, it is merely the process of forming a thin film on a substrate. There may be different growth modes depending on the type of substrate, the deposition temperature, the deposition method, and the like, but they are all just variations of the same process and do not amount to being different species. In at least ¶¶[0034]-[0035] Li teaches that the substrate (10) is a single crystal semiconductor such as Si and, consequently, provides a template suitable for epitaxial growth. Then in at least ¶¶[0039]-[0040] Li further teaches that the logic and memory devices (14) formed on the substrate (10) include arrays of CMOS transistors and capacitors which are fabricated using conventional techniques such as deposition and patterning of the transistor elements. While Li does not specifically mention or use the term “epitaxial,” CMOS transistors and capacitors formed on single crystal Si substrates universally involve a process which requires epitaxial growth of one or more layers onto the substrate or, alternatively, an ordinary artisan would be motivated to utilize epitaxial growth to produce higher quality CMOS transistors and capacitors thereupon. The Examiner’s position is supported by at least Figs. 30A-E and ¶¶[0180]-[0182] of U.S. Patent Appl. Publ. No. 2014/0038392 to Yonehara, et al. (“Yonehara”) which teach that an epitaxial Si active layer is grown on the substrate and that CMOS pixels are processed in the epitaxial Si layer. Additionally, in Figs. 31B(1)-(3) and ¶¶[0183]-[0186] Yonehara further teaches that SOI wafers may be produced using a process which involves the growth of an epitaxial Si layer on the substrate. Thus, it is the Examiner’s position that the process of Li necessarily involves the formation of one or more epitaxial layers or, alternatively, an ordinary artisan would be motivated to form one or more epitaxial layers as part of a method of forming the desired CMOS devices thereupon. Applicants then argue that an ordinary artisan would not combine the method of Henley with the teachings of Li because the use of ion implantation to produce the cleavage plane would damage the electronic devices formed on the surface of the substrate in Li. Id. at pp. 8-9. Applicants’ argument is noted, but is moot in view of the grounds of rejection set forth in this Office Action which is being utilized as a result of applicants’ amendment to claim 10. The teachings of Yonehara, which were previously relied upon to teach the limitations recited in claims 138 and 139, have been relied upon to teach that the use of a laser to form a subsurface damaged region by irradiating the substrate from a back surface such that electronic devices formed on a front surface are not impacted is known in the art. In this case applicants’ argument is moot as laser irradiation from a back surface to produce the desired cleavage plane does not damage electronics formed on the front surface. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH A BRATLAND JR whose telephone number is (571)270-1604. The examiner can normally be reached Monday- Friday, 7:30 am to 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kaj Olsen can be reached on (571) 272-1344. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KENNETH A BRATLAND JR/Primary Examiner, Art Unit 1714
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Prosecution Timeline

Show 8 earlier events
Jun 27, 2025
Response Filed
Oct 17, 2025
Request for Continued Examination
Oct 21, 2025
Response after Non-Final Action
Feb 17, 2026
Request for Continued Examination
Feb 20, 2026
Response after Non-Final Action
Feb 27, 2026
Non-Final Rejection mailed — §103, §112
Jun 26, 2026
Response Filed
Jul 15, 2026
Final Rejection mailed — §103, §112 (current)

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