DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1-6, 8, 10-11, 14-15, 20-23 and 27 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wei et al. (PG Pub. No. US 2019 / 0096830 A1 ) . Regarding claim 1 , Wei teaches a device comprising: an interconnect structure (¶ 0013: 100a) having an upper surface (bottom surface of fig. 1G) prepared for direct bonding (fig. 1I: surface of 100a configured for direct bonding to 200a); a first contact pad (¶ 0033: 116) extending to a first depth below the upper surface (fig. 1G: 116 extends to depth D2); and a second contact pad (¶ 0032: 114) extending to a second depth below the upper surface (fig. 1G: 114 extends to depth D1), the second depth being less than the first depth (¶ 0037: second depth D2 is greater than the first depth D1 ). Regarding claim 2 , Wei teaches the device of Claim 1, wherein the first contact pad comprises an active pad electrically connected to an underlying interconnect (¶ 0034: 116 electrically connected to conductive layer 104). Regarding claim 3 , Wei teaches the device of Claim 2, wherein the first contact pad directly connects to the underlying interconnect without an intervening via (fig. 1G: 116 directly connects to 104). Regarding claim 4 , Wei teaches the device of Claim 2, wherein the second contact pad comprises a dummy pad (¶ 0032) not electrically connected to the underlying interconnect (fig. 1G: 114 not electrically connected to 104). Regarding claim 5 , Wei teaches the device of Claim 1, wherein the first contact pad and the second contact pad are made of metal (¶¶ 0030, 0032, 0034: 116 and 114 comprise metal 112). Regarding claim 6 , Wei teaches the device of Claim 5, wherein the first contact pad and the second contact pad are made of copper (¶ 0030: 112 comprises copper). Regarding claim 8 , Wei teaches the device of Claim 1, wherein the first contact pad is disposed in an opening (¶ 0034: 116 formed in trench 113) having sidewalls that have no corner (fig. 1E: 113 has sidewalls with no corner). Regarding claim 10 , Wei teaches the device of Claim 1, wherein the first pad and the second pad are approximately uniformly distributed on the upper surface of the interconnect structure (fig. 1G: 116 and 114 approximately uniformly distributed). Regarding claim 11 , Wei teaches the device of Claim 1, wherein the first pad and the second pad are approximately uniformly distributed in the interconnect structure (fig. 1G: 116 and 114 approximately uniformly distributed in 100a). Regarding claim 14 , Wei teaches the device of Claim 1, wherein the interconnect structure comprises a first dielectric layer comprising the upper surface (¶ 0020 & fig. 1G: 110), the first and second contact pads extending into the first dielectric layer (fig. 1G). Regarding claim 15 , Wei teaches a bonded structure (¶ 0013 & fig. 1I: 300a) comprising the device of Claim 14 (100a) and a second element (¶ 0013: 200a) comprising a second dielectric layer (¶ 0033: 210) and a third contact pad (¶ 0040: 216) at least partially embedded in the second dielectric layer (fig. 1I: 216 partially embedded in 210), wherein the first dielectric layer is directly bonded to the second dielectric layer without an adhesive (¶ 0046: 110 bonded to 210) and the first contact pad is directly bonded to the third contact pad without an adhesive (¶ 0046: 116 bonded to 216). Regarding claim 20 , Wei teaches a device comprising: an interconnect structure (¶ 0013: 100a) having a surface prepared for direct bonding (fig. 1I: bottom surface of 100a suitable for direct bonding); and a plurality of pads (¶¶ 0032-0033: 114, 116) embedded in the interconnect structure (figs. 1G, 2: 114, 116 embedded in 100a), the plurality of pads comprising: a first plurality of active pads (fig. 2: plurality of 116); and a second plurality of dummy pads (fig. 2: plurality of 114), the dummy pads having a smaller thickness than the active pads (¶¶ 0036-0037 & fig. 1G: 114 has thickness D1 less than 116 thickness D1). Regarding claim 21 , Wei teaches the device of Claim 20, wherein each of the first plurality of active pads electrically connects to an underlying interconnect (¶ 0035 & fig. 1G: 116 electrically connected to conductive layer 104) . Regarding claim 22 , Wei teaches the device of Claim 21, wherein each of the first plurality of active pads directly connects to the underlying interconnect without an intervening via (¶ 0035 & fig. 1G: 116 directly connected to conductive layer 104) . Regarding claim 23 , Wei teaches the device of Claim 22, wherein each of the second plurality of dummy pads is not electrically connected to the underlying interconnect (fig. 1G: 114 not electrically connected to 104) . Regarding claim 27 , Wei teaches the device of Claim 20, wherein each active pad has sidewalls that are unitary (fig. 1G: 116 comprises unitary sidewalls) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Wei . Regarding claims 12-13, Wei teaches the device of claim 1, wherein the first depth is greater than the second depth (¶ 0037: D2>D1). Wei does not explicitly teach wherein a ratio of the second depth to the first depth is greater than 85 % . However, We teaches the second depth in a range of about 0.1 um to about 0.7 um, and the first depth in a range of about 3 um to about 20 um (¶¶ 0036-0037). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the depth ratio of Wei, as a means to optimize overall thickness of the first semiconductor device 100a since the first thickness T1 of the first bonding layer 110 is reduced. In addition, the fabrication time and cost are reduced due to the thinner first bonding layer (Wei, ¶ 0024). Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, adjusting the layer thickness and corresponding contact pad depths of Wei to arrive at the claimed range of “ a ratio of the second depth to the first depth is greater than 85 % ” would be a matter of routine skill. Claim s 43-44 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of Fujii et al. (PG Pub. No. US 2014 / 0145338 A1 ). Regarding claim 43 , Wei teaches a device comprising: a device portion (¶ 0068: 502) comprising a circuitry (510); an interconnect layer (¶ 0073: 520/106/108/110) disposed on the device portion (fig. 5A: 520/106/108/110 disposed on 502) and having an upper bonding surface (bottom surface of fig. 5A) prepared for direct hybrid bonding to a second element (fig. 5C: bottom surface of 110 suitable for hybrid bonding to 210 of 600), the interconnect layer comprising: one or more non-conductive layers (¶¶ 0072-0076: 514, 522, 106, 108 and/or 110) on the device portion (fig. 5A: 514/522/106/108/110 disposed on 502) , the one or more non-conductive layers having a first cavity (¶ 0055: 113) and a second cavity (¶ 0055: 111) formed therein (fig. 3A: 113 and 111 formed in at least layer 110) ; a buried conductive layer (¶ 00 73 : 104) electrically connected to the circuitry and embedded in the one or more non-conductive layers at a first depth below the upper bonding surface (fig. 5A: 104 embedded in at least layer 522 below bottom surface of 110) ; an electrically functional conductive pad (¶ 00 7 6: via 116 , including electrically conductive material 112 ) disposed in the first cavity and extending from the upper bonding surface through at least a portion of the one or more non- conductive layers to connect to the buried conductive layer (fig. 5A: 116 disposed in trench 113 and extends through 106/108/110 to 104) , the first cavity delimited by a continuous sidewall of the one or more non-conductive layers extending from the upper bonding surface (fig. 3A: 113 delimited by continuous sidewall of 106, 108 and 110) ; and an electrically non-functional conductive pad (¶ 0056: 114) disposed in the second cavity and extending from the upper bonding surface through at least a portion of the one or more non-conductive layers (figs. 3A-3B, 5A: 114 disposed in trench 114 and extending from bottom surface of 110 through 110) , the electrically non-functional conductive pad terminating at a second depth that is less than the first depth (¶ 0037: depth D1 of 114 less than depth D2 of 116) . Wei does not explicitly teach the buried conductive layer is electrically connected to the circuitry . Fujii teaches a device (fig. 6: 600) including a buried conductive layer (¶¶ 0066, 0078: wiring lines 21, similar to 104 of Wei) electrically connected to circuitry (¶ 0077: transistor 34, similar to 510 of Wei) and an electrically functional conductive pad (¶ 0048 & fig. 6: pad 4, similar to 116 of Wei). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to is electrically connect the buried conductive layer to the circuitry , as a means to transfer signals from the circuitry of a pixel region (12 of Wei) to signal processing circuitry ( Fujii , ¶ 0082). Regarding claim 43 , Wei in view of Fujii teaches t he device of Claim 43, wherein the electrically functional conductive pad directly connects to the buried conductive layer without an intervening via (Wei, fig. 5A: 116 directly connects to 104) . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Watanabe (PG Pub. No. US 2021 / 0280545 A1 ) teaches a device (2) comprising an interconnect structure (10) having an upper surface (bottom surface of 15) prepared for direct bonding (¶ 0069), a first contact pad (23) extending to a first depth below the upper surface (fig. 4), and a second contact pad (24) extending to a second depth below the upper surface (fig. 4), the second depth being less than the first depth (¶ 0066). Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT BRIAN TURNER whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5411 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8am-5pm . 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