Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Request for Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/11/2025 has been entered.
DETAILED ACTION
Response to Amendment
This office action is in response to Amendment filed on 06/17/2025.
Claim 1 has been amended.
Claims 1-8 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0125500, hereinafter as Kim ‘500) in view of Li (US 2017/0148884, hereinafter as Li ‘884) and further in view of Kim (US 2016/0035805, hereinafter as Kim ‘805).
Regarding Claim 1, Kim ‘500 teaches a method of manufacturing a display apparatus, the method comprising:
forming a semiconductor layer (Fig. 6A, (A41/A42); [0138]) on a substrate (410; [0133]);
forming a first gate insulating layer (Fig. 6A, (413); [0135]) so as to cover the semiconductor layer;
forming a gate electrode (Fig. 6A, (G41/G42); [0135]) on the gate insulating layer, such that the gate electrode at least partially overlaps the semiconductor layer;
forming an interlayer insulating layer (Fig. 6B, (415/417); [0146]) on the gate electrode;
forming a contact hole (Fig. 6E, (CH4); [0146]) through the gate insulating layer and the interlayer insulating layer (417) to expose a portion of the semiconductor layer;
forming an electrode layer (Fig. 6D, (metal layer (418’)); [0127]) on the interlayer insulating layer (417). Examiner consider the metal layer 418’ is the electrode layer,
forming a photoresist pattern (Fig. 6E, (PR3); [0149]) on the electrode layer (418’) corresponding to a first portion of the interlayer insulating layer (417);
etching the electrode layer (418’) using the photoresist pattern as a mask (see para. [0150]);
Thus, Kim ‘500 is shown to teach all the features of the claim with the exception of explicitly the feature: “the electrode layer being electrically connected to the semiconductor layer through the contact hole; and etching a second portion of the interlayer insulating layer using the photoresist pattern, the second portion extending from the first portion of the interlayer insulating layer”.
Li ‘884 teaches the electrode layer (Fig. 1F, (310/320); [0045]) being electrically connected to the semiconductor layer (100; [0042]) through the contact hole; and etching a second portion of the interlayer insulating layer (Fig. 2A, (220; [0042]) using the photoresist pattern (not shown; see Fig. 2A), the second portion extending from the first portion of the interlayer insulating layer (220) (see Fig. 2A). It would obviously appear that the interlayer insulating layer has been etched using the photoresist pattern.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘500 by having the electrode layer being electrically connected to the semiconductor layer through the contact hole; and etching a second portion of the interlayer insulating layer using the photoresist pattern, the second portion extending from the first portion of the interlayer insulating layer in order to fabricate the display panel with lower cost (see para. [0077]) as suggested by Li ‘884.
Thus, Kim ‘500 and Li ‘884 are shown to teach all the features of the claim with the exception of explicitly the feature: “forming a second gate insulating layer over the gate electrode; forming an upper electrode over the second gate insulating layer and the gate electrode, such that the gate electrode and the upper electrode constitute electrodes of a capacitor”.
Kim ‘805 teaches forming a second gate insulating layer (Fig. 5, (GI2); [0080]) over the gate electrode (Fig. 5, (G1); [0080]); forming an upper electrode (Fig. 5, (C2); [0087]) over the second gate insulating layer (GI2) and the gate electrode (G1), such that the gate electrode (G1) and the upper electrode (C2) constitute electrodes of a capacitor (Cst; [0087]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘500 and Li ‘884 by forming a second gate insulating layer over the gate electrode; forming an upper electrode over the second gate insulating layer and the gate electrode, such that the gate electrode and the upper electrode constitute electrodes of a capacitor in order to ensure sufficiently a storage capacity of the storage capacitor Cst (see para. [0085) as suggested by Kim ‘805.
Regarding Claim 4, Kim ‘500, Li ‘884 and Kim ‘805 are shown to teach all the features of the claim with the exception of explicitly the features: “cleaning the electrode layer concurrently with the etching of the second portion of the interlayer insulating layer”.
However, it has been held to be within the general skill of a worker in the art to clean the electrode layer concurrently with the etching of the second portion of the interlayer insulating layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to clean the electrode layer concurrently with the etching of the second portion of the interlayer insulating layer in order to allow a good flow with the other steps in the fabrication process.
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Regarding Claim 7, Li ‘884 teaches removing the photoresist pattern (see para. [0049]).
Regarding Claim 8, Kim ‘500 teaches a top surface of the first portion is greater than a width of a bottom surface of the electrode layer (see Fig. 3).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘500, Li ‘884 and Kim ‘805 as applied to claim 1 above, and further in view of Jeong (US 2019/0355799, hereinafter as Jeon ‘799).
Regarding Claim 2, Kim ‘500, Li ‘884 and Kim ‘805 are shown to teach all the features of the claim with the exception of explicitly the features: “a first area, a second area surrounding the first area, and a third area between the first area and the second area, and the gate insulating layer and the interlayer insulating layer located on the first area are removed together when the contact hole is formed”.
Jeon ‘799 teaches a first area, a second area surrounding the first area, and a third area between the first area and the second area, and the gate insulating layer (125; [0035]) and the interlayer insulating layer (135; [0035]) located on the first area are removed together (formed at
substantially the same time; [0077]) when the contact hole is formed (see Fig. 9).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘500, Li ‘884 and Kim ‘805 by having a first area, a second area surrounding the first area, and a third area between the first area and the second area, and the gate insulating layer and the interlayer insulating layer located on the first area are removed together when the contact hole is formed in order to using a single processing step (see para. [0077]) as suggested by Jeon ‘799.
Regarding Claim 3, Jeon ‘799 teaches forming a buffer layer (Fig. 9, (115); [0036]) between the substrate (110; [0036]) and the semiconductor layer (120; [0035]), wherein the buffer layer (115) located on the first area is etched together when part of the interlayer insulating layer (135) is etched (see Fig. 9).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘500, Li ‘884 and Kim ‘805 as applied to claim 1 above, and further in view of Yamazaki (US 2009/0045403, hereinafter as Yama ‘403).
Regarding Claim 5, Kim ‘500, Li ‘884 and Kim ‘805 are shown to teach all the features of the claim with the exception of explicitly the features: “etching the interlayer insulating layer using carbon tetrafluoride (CF4)”.
Yama ‘403 teaches etching the interlayer insulating layer using carbon tetrafluoride (CF4) (see para. [0110]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘500, Li ‘884 and Kim ‘805 by etching the interlayer insulating layer using carbon tetrafluoride (CF4) in order to improve the selection ratio with the semiconductor film (see para. [0110]) as suggested by Yama ‘403.
Regarding Claim 6, Kim ‘500 teaches etching the interlayer insulating layer (see Fig. 6E).
Yama ‘403 teaches applying a bias voltage with the etching (see para. [0056]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Kim et al. (US 2016/0093647 A1)
Kim (US 2015/0108454 A1)
Kim et al. (US 2010/0308326 A1)
Miyagi et al. (US 2005/0051776 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893