Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-7 in the reply filed on December 04th, 2025, are acknowledged. Claim 1 has been amended. Claims 1-7 are pending.
Action on merits of claims 1-7 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-2 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2013/0168685, hereinafter as Hsu ‘685) in view of Ikeda (JPH 06120258, hereinafter as Iked ‘258) and further in view of Green (US 2014/0239346, hereinafter as Green ‘346).
Regarding Claim 1, Hsu ‘685 teaches a method for fabricating high electron mobility transistor (HEMT), comprising:
forming a buffer layer (Fig. 8, (104); [0015]) on a substrate (102; [0015]);
forming a barrier layer (Fig. 8, (106); [0016]) on the buffer layer (104);
forming a first hard mask (Fig. 8, (110); [0019]) on the barrier layer (106);
forming a second hard mask (Fig. 8, (114); [0025]) on the first hard mask;
patterning the second hard mask (114), the first hard mask (110), the barrier layer (106), and the buffer layer (104) (not shown; see para. [0049]); wherein the barrier layer (106), and an upper portion of the buffer layer (104) comprise a first width and a lower portion of the buff layer (104) comprises a second width (see Fig. 8);
removing (by an etching process; [0049]) the second hard mask (114) and the first hard mask (110) to form a recess (an opening, Fig. 9, (118); [0049]); and
forming a p-type semiconductor layer (Fig. 10, (120); [0050]) on the barrier layer (106).
Thus, Hsu ‘685 is shown to teach all the features of the claim with the exception of explicitly the limitations: “patterning the second hard mask, the first hard mask, the barrier layer, and the buffer layer to form a MESA isolation to form a MESA isolation”.
Iked ‘258 teaches patterning the second hard mask (18; [0006]), the first hard mask (17; [0006]), the barrier layer (16; [0006]), and the buffer layer (12; [0006]) to form a MESA isolation (see Fig. 2b; [0024]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Hsu ‘685 by forming a MESA isolation for the advantage of providing a high electron mobility transistor has excellent controllability of the threshold voltage, and enables a device configuration with good reproducibility to be obtained (see para. [0013]) as suggested by Iked ‘258.
Thus, Hsu ‘685 and Iked ‘258 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the second hard mask and the first hard mask made of different dielectric materials; the second hard mask, the first hard mask, the barrier layer, and an upper portion of the buffer layer comprise a first width and a lower portion of the buff layer comprises a second width”.
Green ‘346 teaches the second hard mask (SiN, Fig. 5, (516); [0066]) and the first hard mask (Al2O3, Fig. 5, (518); [0066]) made of different dielectric materials; and the second hard mask (516), the first hard mask (518), the barrier layer (BARRIER), and an upper portion of the buffer layer (buffer) comprise a first width (B) and a lower portion of the buffer layer (buffer) comprises a second width (A) (see Fig. 5_Annotated).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Hsu ‘685 and Iked ‘258 by having the second hard mask and the first hard mask made of different dielectric materials; the second hard mask, the first hard mask, the barrier layer, and an upper portion of the buffer layer comprise a first width and a lower portion of the buff layer comprises a second width in order to fabricate using the same fabrication process flow (see para. [0014]) as suggested by Green ‘346.
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Figs. 8-9 (Hsu ‘685)
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Fig. 2 (Iked ‘258)
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[AltContent: textbox (A)] Fig. 5 (Green ‘346_Annotated)
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Regarding Claim 2, Hsu ‘685 teaches forming a third hard mask (not shown) on the second hard mask and sidewalls of the barrier layer and the buffer layer; and removing the third hard mask and the second hard mask (through the lithography and etching process [0055]);
forming the p-type semiconductor layer (120) in the recess and on the barrier layer (106);
removing the third hard mask and the second hard mask (through the lithography and etching process [0055]).
forming a gate electrode (124; [0028]) on the p-type semiconductor layer (120); and
Green ‘346 teaches forming a passivation layer (Fig. 5, (516); [0066]) on the first hard mask (518; [0066]). Examiner considers the dielectric layer (516) is the passivation layer and the dielectric layer (518; [0042]) is the first hard mask.
Regarding Claim 4, Hsu ‘685, Iked ‘258 and Green ‘346 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the second hard mask and the third hard mask comprise a same material”.
However, it has been held to be within the general skill of a worker in the art to select a material for the second/third hard mask such that the second hard mask and the third hard mask comprise a same material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select the second hard mask material is same the third hard mask material when this allows a good flow with the other steps in the fabrication process.
Regarding Claim 5, Hsu ‘685 teaches the first hard mask (e.g. SiO2 (110); [0038]) and the second hard mask (e.g. Si3N4 (114); [0047]) comprise different materials.
Regarding Claim 6, Dora ‘320 teaches the barrier layer (12; [0040]) comprises AlxGa1-xN.
Further. it has been held to be within the general skill of a worker in the art to select a material (e.g. AlxGa1-xN) for the barrier layer on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select a material (e.g. AlxGa1-xN) for the barrier layer when this improves the performance of the HEMT device.
Regarding Claim 7, Hsu ‘685 teaches the buffer layer (104; [0015]) comprises gallium nitride (GaN).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘685, Iked ‘258 and Dora ‘320 as applied to claim 2 above, and further in view of Lidow (US 2010/0258841, hereinafter as Lido ‘841).
Regarding Claim 3, Green ‘346 teaches forming the passivation layer (516) on the first hard mask layer (518) (see Fig. 5).
Thus, Hsu ‘685 Iked ‘258 and Green ‘346 are shown to teach all the features of the claim with the exception of explicitly the limitations: “forming the passivation layer on the sidewalls of the barrier layer and the buffer layer”.
Lido ‘841 teaches forming the passivation layer (Fig. 1, (107); [0006]) on the sidewalls of the barrier layer (104; [0006]) and the buffer layer (103; [0006]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Hsu ‘685 Iked ‘258 and Green ‘346 by forming the passivation layer on the sidewalls of the barrier layer and the buffer layer in order to isolate the HEMT devices (see para. [0006]) as suggested by Lido ‘841.
Response to Arguments
Applicant’s arguments with respect to claims 1-7, filed on December 04th, 2025, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893