Prosecution Insights
Last updated: October 02, 2026
Application No. 18/395,760

MIM CAPACITOR DISPOSED IN MODIFIED DUAL DAMASCENE STRUCTURE AND FABRICATING METHOD OF THE SAME

Final Rejection §103
Filed
Dec 26, 2023
Priority
Dec 01, 2023 — TW 112146858
Examiner
HRNJIC, ADIN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
2 (Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
6m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allowance Rate
39 granted / 59 resolved
-1.9% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
29 currently pending
Career history
105
Total Applications
across all art units

Statute-Specific Performance

§103
56.6%
+16.6% vs TC avg
§102
21.7%
-18.3% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 59 resolved cases

Office Action

§103
Detailed Action This office action is in response to the amendment filed on June 3rd, 2026. Claims 1-13 are pending. Claims 9-13 have been withdrawn. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed June 3rd, 2026, have been fully considered but they are not persuasive. Applicant argues (pgs. 7-13, “Remarks”) that Chou and Liu fail to teach the limitations presented in amended Claim 1. However, as seen below, Claim 1 is now rejected by the combination of Chou and Wei. Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection. Applicant’s amendments have overcome the 35 U.S.C. 112(b) rejections of the previous office action. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis. Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al. (2017/0271434 A1; hereinafter Chou) in view of Wei et al. (2018/0019205 A1; hereinafter Wei). Regarding Claim 1, Chou (fig. 1) teaches a metal-insulator-metal (MIM) capacitor ([0018], 116) disposed in a modified dual damascene structure ([0020], dual damascene structure), comprising: a dielectric layer ([0017], 110); a first modified dual damascene structure ([0020], 110b, 118b) disposed in the dielectric layer (110), wherein the first modified dual damascene structure (110b, 118b) comprises: a trench (118b); a hole (110b), wherein the hole (110b) connects to the trench (118b) and the hole comprises a funnel profile, wherein the funnel profile comprises a wide hole and a narrow hole, the wide hole comprises a first sidewall, the narrow hole comprises a second sidewall, and the first sidewall and the second sidewall have different slopes; the MIM capacitor (116) disposed in the first modified dual damascene structure (110b, 118b); and a first copper layer ([0018], 122b, [0033], 122b may be copper) disposed in the first modified dual damascene structure (110b, 118b) and on the MIM capacitor (116). Chou doesn’t teach the hole comprises a funnel profile, wherein the funnel profile comprises a wide hole and a narrow hole, the wide hole comprises a first sidewall, the narrow hole comprises a second sidewall, and the first sidewall and the second sidewall have different slopes. However, Wei (fig. 6) teaches the hole ([0022], 58, 52) comprises a funnel profile ([0022]), wherein the funnel profile comprises a wide hole (58) and a narrow hole (52), the wide hole (58) comprises a first sidewall ([0023], 64), the narrow hole (52) comprises a second sidewall ([0023], 62), and the first sidewall (64) and the second sidewall (62) have different slopes (see annotated fig. 4). Wei also teaches that a funnel-shaped via, or in other words a via with angled sidewalls, resolves the issue of forming voids when performing a dual damascene process ([0028]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the MIM capacitor of Chou to include the angle of Wei to resolve the issue of forming voids when performing a dual damascene process. Regarding Claim 2, Wei (fig. 6) teaches the MIM capacitor disposed in a modified dual damascene structure of claim 1, wherein a width of the wide hole (58) is greater (see fig. 6) than a width of the narrow hole (52). Regarding Claim 3, Wei (fig. 6) teaches the MIM capacitor disposed in a modified dual damascene structure of claim 2, wherein the wide hole (58) connects the trench ([0022], 60) and the narrow hole (52), and the wide hole (58) converges from the trench (60) to the narrow hole (52). Regarding Claim 4, Wei (fig. 6) teaches the MIM capacitor disposed in a modified dual damascene structure of claim 2, wherein: the first sidewall (64) faces the dielectric layer ([0016], 28), the dielectric layer (28) comprises a top surface (top surface of 28), a horizontal direction (left to right) is parallel to the top surface (top surface of 28), there is an angle disposed between the first sidewall (64) and the horizontal direction (left to right), and the angle is between 60 and 80 degrees ([0024], angle may be 60 degrees). Regarding Claim 5, Chou (fig. 1) teaches the MIM capacitor disposed in a modified dual damascene structure of claim 1, further comprising: a second modified dual damascene structure ([0020], 110a, 118a) disposed in the dielectric layer (110), wherein a profile of the second modified dual damascene structure (110a, 118a) is the same as a profile of the first modified dual damascene structure (110b, 118b); a barrier ([0021], 120a) covering the second modified dual damascene structure (110a, 118a); and a second copper layer ([0021], 122a, [0033], 122a may be copper) covering the barrier (120a). Regarding Claim 6, Chou (fig. 1) teaches the MIM capacitor disposed in a modified dual damascene structure of claim 5, wherein the MIM capacitor (116) comprises a top electrode ([0021] 120b), a capacitor dielectric layer ([0021], 114b) and a bottom electrode ([0021], 112b) stacked in sequence from bottom to top (see fig. 1), and the top electrode (120b) and the barrier (120a) are made of the same material ([0031], 120 forms both 120a and 120b). Regarding Claim 7, Chou (fig. 1) teaches the MIM capacitor disposed in a modified dual damascene structure of claim 6, wherein the top electrode (120b) comprises tantalum nitride ([0031], TaN) or titanium nitride and the bottom electrode (112a) comprises tantalum ([0027], 112b may be TaN, which comprises tantalum) or titanium. Regarding Claim 8, Chou (fig. 1) teaches the MIM capacitor disposed in a modified dual damascene structure of claim 1, wherein the trench (118b) is disposed on the hole (110a). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Christensen et al. (2018/0145024 A1) teaches a dual damascene MIM capacitor. See fig. 2 and [0030]-[0035]. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.H./Examiner, Art Unit 2817 /ANTONIO B CRITE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Dec 26, 2023
Application Filed
Apr 15, 2026
Non-Final Rejection mailed — §103
Jun 03, 2026
Response Filed
Sep 15, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
76%
With Interview (+9.7%)
3y 4m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 59 resolved cases by this examiner. Grant probability derived from career allowance rate.

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