Prosecution Insights
Last updated: August 17, 2026
Application No. 18/395,777

CONTROLLING METHOD FOR SEMICONDUCTOR PROCESS AUXILIARY APPARATUS, CONTROL ASSEMBLY AND MANUFACTURING SYSTEM

Non-Final OA §103§112
Filed
Dec 26, 2023
Priority
Nov 02, 2023 — CN 202311446708.5
Examiner
MOORE, KARLA A
Art Unit
1716
Tech Center
1700 — Chemical & Materials Engineering
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
43%
Grant Probability
Moderate
1-2
OA Rounds
1y 5m
Est. Remaining
57%
With Interview

Examiner Intelligence

Grants 43% of resolved cases
43%
Career Allowance Rate
337 granted / 781 resolved
-21.9% vs TC avg
Moderate +14% lift
Without
With
+14.1%
Interview Lift
resolved cases with interview
Typical timeline
4y 1m
Avg Prosecution
66 currently pending
Career history
855
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
51.0%
+11.0% vs TC avg
§102
14.3%
-25.7% vs TC avg
§112
28.9%
-11.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 781 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group II, claims 9-20, in the reply filed on 21 May 2026 is acknowledged. Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i). Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: Claim 9 and 17: energy-saving trigger analyzing unit which has been interpreted as a circuit, a chip, a circuit board or a storage device, any of which stores program codes, and equivalents thereof, as set forth in the specification at para. 20. Claim 9 and 17: energy-saving control unit has been interpreted as a circuit, a chip, a circuit board or a storage device, any of which stores program codes, and equivalents thereof, as set forth in the specification at para. 21. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11 recites “a plurality of manufacturing parameters” without relating the same to the previously recited “at least one manufacturing parameter”. In order to expedite examination, Examiner has assumed the claim was meant to also include language stating the at least one manufacturing parameter is a plurality of manufacturing parameters and has examined accordingly. Clarification and/or correction is requested. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2013/0171919 to Shinohara et al. in view of U.S. Patent Pub. No. 2023/0095537 to Takahashi et al. Regarding claim 9: Shinohara et al. disclose a control assembly for controlling at least one semiconductor process auxiliary apparatus substantially as claimed and comprising: an energy-saving trigger analyzing unit (6), used for generating an energy adjusting signal according to the at least one manufacturing parameter of a semiconductor manufacturing process apparatus; and an energy-saving control unit (e.g. Fig. 7, vacuum pump apparatus controller [not numbered], exhaust gas treatment apparatus controller [not numbered, and diluent N2 controller unit [not numbered]), used for generating an auxiliary apparatus controlling signal according to the energy adjusting signal, and used for controlling the at least one semiconductor process auxiliary apparatus according to the auxiliary apparatus controlling signal. However, while Shinohara et al. do disclose a controller and a control units as the energy-saving trigger analyzing unit and the energy-saving control unit respectively, Shinohara et al. fail to explicitly disclose the structure of the energy-saving trigger analyzing unit and/or the energy-saving control unit as a circuit, a chip, a circuit board or a storage device, any of which stores program codes and equivalents thereof. Takahashi et al. disclose a manufacturing system having a control assembly having a controller or control unit as a microprocessor (a computer) including a CPU and storage connected thereto for the purpose of executing a process according to a programming in the storage, whereby the manufacturing system performs a desired process under control of the microprocessor (a computer) including a CPU and storage (see, e.g., paras. 41 and 42). Thus, it would have been obvious to one of ordinary skill in the art before Applicant’s invention was effectively filed to have provided the controller and control unit representing the energy-saving trigger analyzing unit and the energy-saving control unit as a microprocessor (a computer) including a CPU and storage connected thereto in Shinohara et al. in order perform the disclosed processes as taught by Takahashi et al. With respect to claim 10, in Shinohara et al., the energy-saving trigger analyzing unit is used for generating a process determination result based on whether one manufacturing parameter of the at least one manufacturing parameter meets a process determination condition (amount of powder build-up), and used for generating the energy adjusting signal according to the process determination result. With respect to claim 11, in Shinohara et al., with repeated use, the energy-saving trigger analyzing unit is used for generating a process determination result based on whether a plurality of manufacturing parameters of the at least one manufacturing parameters meet any process determination conditions, and used for generating the energy adjusting signal according to the process determination result. With respect to claim 12, in Shinohara et al., the at least one manufacturing parameter includes an energy setting value, a temperature setting value, a pressure setting value (as measured by 28), or a gas valve position. With respect to claim 13, in Shinohara et al., the semiconductor manufacturing process apparatus may be used to perform semiconductor manufacturing processes on wafers, wherein the at least one semiconductor process auxiliary apparatus is connected to the semiconductor manufacturing apparatus to provide a processing environment for the semiconductor manufacturing process apparatus (see, e.g., abstract). With respect to claim 14, in Shinohara et al., the at least one semiconductor process auxiliary apparatus includes a plurality of semiconductor auxiliary apparatus (vacuum pump apparatus 3, exhaust gas treatment apparatus 5, and diluent N2 unit 4), and the energy-saving control unit is used for performing different controls on the plurality of semiconductor process auxiliary apparatus according to the auxiliary apparatus controlling signal. See, e.g., Fig. 7 and accompany text. With respect to claim 15, in Shinohara et al., the semiconductor manufacturing process apparatus is a lithography apparatus, an etching apparatus, a thin film deposition apparatus or a diffusion apparatus. See, e.g., paragraph 2. With respect to claim 16, in Shinohara et al., the at least one semiconductor process auxiliary apparatus is a pump (3) or a scrubber (5). Regarding claim 17, Shinohara et al. disclose a manufacturing system substantially as claimed and comprising: a semiconductor manufacturing process apparatus (Figs. 1-5 and 7, 1), having at least one manufacturing parameter (pressure as measured by sensor 28); at least one semiconductor process auxiliary apparatus (e.g. 3, 4 and 5); and a control assembly (see, e.g., Figs. 7), including: an energy-saving trigger analyzing unit (6), used for generating an energy adjusting signal according to the at least one manufacturing parameter of a semiconductor manufacturing process apparatus; and an energy-saving control unit (e.g. Fig. 7, vacuum pump apparatus controller [not numbered], exhaust gas treatment apparatus controller [not numbered, and diluent N2 controller unit [not numbered]), used for generating an auxiliary apparatus controlling signal according to the energy adjusting signal, and used for controlling the at least one semiconductor process auxiliary apparatus according to the auxiliary apparatus controlling signal. However, while Shinohara et al. do disclose a controller and a control unit as the energy-saving trigger analyzing unit and the energy-saving control unit respectively, Shinohara et al. fail to explicitly disclose the structure of the energy-saving trigger analyzing unit and/or the energy-saving control unit as a circuit, a chip, a circuit board or a storage device, any of which stores program codes and equivalents thereof. Takahashi et al. disclose a manufacturing system having a control assembly having a controller or control unit as a microprocessor (a computer) including a CPU and storage connected thereto for the purpose of executing a process according to a programming in the storage, whereby the manufacturing system performs a desired process under control of the microprocessor (a computer) including a CPU and storage (see, e.g., paras. 41 and 42). Thus, it would have been obvious to one of ordinary skill in the art before Applicant’s invention was effectively filed to have provided the controller and control unit representing the energy-saving trigger analyzing unit and the energy-saving control unit as a microprocessor (a computer) including a CPU and storage connected thereto in Shinohara et al. in order perform the disclosed processes as taught by Takahashi et al. With respect to claim 18, in Shinohara et al., the energy-saving trigger analyzing unit is used for generating a process determination result based on whether one manufacturing parameter of the at least one manufacturing parameter meets a process determination condition (amount of powder build-up), and used for generating the energy adjusting signal according to the process determination result. With respect to claim 19, in Shinohara et al., with repeated use, the energy-saving trigger analyzing unit is used for generating a process determination result based on whether a plurality of manufacturing parameters of the at least one manufacturing parameters meet any process determination condition of a plurality of process determination conditions, and used for generating the energy adjusting signal according to the process determination result. With respect to claim 20, in Shinohara et al., the at least one semiconductor process auxiliary apparatus includes a plurality of semiconductor auxiliary apparatus (vacuum pump apparatus 3, exhaust gas treatment apparatus 5, and diluent N2 unit 4), and the energy-saving control unit is used for performing different controls on the plurality of semiconductor process auxiliary apparatus according to the auxiliary apparatus controlling signal. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. KR 101314187, KR 102053931, USP Pub. 2003/0158705, and USP Pub. 2004/0143418 disclose manufacturing systems including a control assembly for an auxiliary apparatus thereof. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KARLA MOORE whose telephone number is (571)272-1440. The examiner can normally be reached Monday-Friday, 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PARVIZ HASSANZADEH can be reached at (571) 272-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KARLA A MOORE/Primary Examiner, Art Unit 1716
Read full office action

Prosecution Timeline

Dec 26, 2023
Application Filed
Jul 17, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
43%
Grant Probability
57%
With Interview (+14.1%)
4y 1m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 781 resolved cases by this examiner. Grant probability derived from career allowance rate.

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