DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II and Species I in the reply filed on 03/04/2026 is acknowledged.
Claims 1-16 are now canceled; Claims 21-36 are newly-added.
Claims 17-36 have been fully considered in Examination.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 01/28/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 35 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 35 recites the limitation "forming the isolation structure" in line 1. There is insufficient antecedent basis for this limitation in the claim. There is no prior recitation of “an isolation structure” in claim 30 on which claim 35 depends, or elsewhere in claim 35, rendering it unclear if “the isolation structure” refers to a previously-recited element or another structure. Therefore, for the purposes of Examination, “forming the isolation structure” in claim 35 has been interpreted as --- forming an isolation structure ---.
Claim 35 recites the limitation "the second side of the first semiconductor substrate" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. There is no prior recitation of “a second side of the first semiconductor substrate” in claim 30 on which claim 35 depends, or elsewhere in claim 35, rendering it unclear if “the second side” refers to a previously-recited side or another side. Therefore, for the purposes of Examination, “"the second side of the first semiconductor substrate" in claim 35 has been interpreted as --- a second side of the first semiconductor substrate ---.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-21 and 24-28 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Baek (U.S. PG Pub No US2025/0151445A1).
Regarding claim 17, Baek teaches a method [0135, 0142, 0156] of making an image sensor (17) fig. 13 [0134], the method comprising:
providing a first semiconductor substrate (102) fig. 15 [0136] and a second semiconductor substrate (202) fig. 19 [0143];
forming a grid isolation structure (106) fig. 15 [0137] in the first semiconductor substrate (102) so as to define cells (‘pixels’ of APS) fig. 15 [0136], wherein the cells (‘pixels’) are portions of the first semiconductor substrate (102 that are laterally surrounded by segments of the grid isolation structure (106) (see annotated fig. 13 for designation of a single-pixel-cell);
forming floating diffusion regions (110) fig. 15 [0136] within the cells (‘pixels’);
forming a first metal interconnect structure (comprising 150, 152, 154, 162 in 142) fig. 17 [0141, 0073] (152, 154, 162 may be formed of copper) [0073-0074] on (supported by) the first semiconductor substrate (102);
forming source followers (SFs) (210a-I) fig. 13 [0077] (refer to annotated fig. 13 below for designation of SF), select gate transistors (210b serving as “selection transistor” – not explicitly shown) fig. 13 [0077], dual conversion gain transistors (DCG) transistors (210a-II) fig. 13 [0077] (refer to annotated fig. 13 below for designation of DCG), and reset transistors (210b) fig. 13 [0077] on (supported by) the second semiconductor substrate (202) (each of these pixel transistors included on second substrate 202 per pixel [0046, 0059]; refer to fig. 20 [0144] for transistor formation step), wherein there is one SF (210a-I) for each floating diffusion region (110) (see annotated fig. 13 below);
forming a second metal interconnect structure (comprising 262 in 222) fig. 29 [0154] (262 formed of copper) [0157] on (supported by) the second semiconductor substrate (202); and
coupling (through electrically connected metal structures [0006-0008]) the first metal interconnect structure (comprising 150, 152, 154 in 142) to the second metal interconnect structure (comprising 262 in 222) (by bonding 162 and 262 [0157]) so that the floating diffusion regions (110) are coupled to respective SFs (210a-1) (refer to annotated fig. 13 below).
[AltContent: arrow][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (One-to-one correspondence between FD’s 110 and SF’s 210a-I) )][AltContent: textbox (210a-II)][AltContent: textbox (210a-I)][AltContent: arrow][AltContent: textbox (Single-cell)]
PNG
media_image1.png
1216
853
media_image1.png
Greyscale
Annotated fig. 13 of Baek
Regarding claim 18, Baek teaches the method [0134-0135, 0142, 0156] of claim 17. Baek also teaches wherein:
the reset transistors (RX) fig. 2 [0050] (corresponding to 210b [0077]) and the DCG transistors (DCX) fig. 2 [0050] (corresponding to 210a-II [0077]) are connected in series [see fig. 2, 0050]; and
coupling the first metal interconnect structure (comprising 150, 152, 154, 162 in 142) fig. 13 [0141, 0073] to the second metal interconnect structure (comprising 262 in 222) fig. 13 [0154] provides wiring (234) fig. 13 [0085, 0089] that couples the floating diffusion regions (110) fig. 13 [0077, 0136] directly to corresponding DCG transistors (210a-II) (210a’s and 110 directly coupled through directly physically adjoined, electrically connected metal structures [0006-0008, 0077, 0089]) (refer to annotated fig. 13 above).
Regarding claim 19, Baek teaches the method [0134-0135, 0142, 0156] of claim 18. Baek also teaches wherein each instance of the wiring [0006-0008, 0077, 0089] that couples [0006-0008, 0077, 0089] the floating diffusion regions (110) fig. 13 [0077, 0136] directly to the corresponding DCG transistors (210a-II) fig. 13 [0077] contains only a single branch (only a single horizontal branch 234 is provided per 234).
Regarding claim 20, Baek teaches the method [0134-0135, 0142, 0156] of claim 17. Baek also teaches further comprising providing a third semiconductor substrate (302) fig. 23 [0148], forming an integrated circuit (310) figs. 23-24 [0148-00149] on the third semiconductor substrate (302), and bonding (through 342/264 bond-pad bonding [see fig. 26, 0151]) the third semiconductor substrate (302) to the second semiconductor substrate (202) (see fig. 13 for completed structure).
Regarding claim 21, Baek teaches a method [0135, 0142, 0156] of making an image sensor (17) fig. 13 [0134], comprising:
receiving a first semiconductor substrate (102) fig. 15 [0136];
forming an array (‘pixels’ / cells of APS) fig. 15 [0136] each comprising a photosensitive area (108) fig. 15 [0136], a floating diffusion region (110) fig. 15 [0136], and a transfer gate (112) fig. 16 [0140, 0066-0068] in the first semiconductor substrate (102);
forming a first metal interconnect structure (comprising 150, 152, 154, 162 in 142) fig. 17 [0141, 0073] (152, 154, 162 may be formed of copper) [0073-0074] comprising a plurality of metallization layers (154) over a first (bottom) side of the first semiconductor substrate (102);
receiving a second semiconductor substrate (202) fig. 19 [0143];
forming source followers (SFs) (210a-I) fig. 13 [0077] (refer to annotated fig. 13 below for designation of SF), select gate transistors (210b serving as “selection transistor” – not explicitly shown) fig. 13 [0077], dual conversion gain transistors (DCG) transistors (210a-II) fig. 13 [0077] (refer to annotated fig. 13 below for designation of DCG), and reset transistors (210b) fig. 13 [0077] on (supported by) the second semiconductor substrate (202) (each of these pixel transistors included on second substrate 202 per pixel [0046, 0059]; refer to fig. 20 [0144] for transistor formation step),
forming a second metal interconnect structure (comprising 262 in 222) fig. 29 [0154] (262 formed of copper) [0157] comprising a plurality of metallization layers (262’s) over the second semiconductor substrate (202); and
bonding [see fig. 31, 0157] the first semiconductor substrate (102) to the second semiconductor substrate (202) via bonding (Cu-Cu bonding) [0157] between the first (comprising 162) and second (comprising 262) metal interconnect structures,
wherein there is a one-to-one correspondence between the floating diffusion regions (110) and the SFs (210a-I) (see annotated fig. 13 below).
[AltContent: arrow][AltContent: arrow][AltContent: textbox (W)][AltContent: textbox (D)][AltContent: connector][AltContent: connector][AltContent: textbox (SC)][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (One-to-one correspondence between FD’s 110 and SF’s 210a-I) )][AltContent: textbox (210a-II)][AltContent: textbox (210a-I)][AltContent: arrow][AltContent: textbox (Single-cell)]
PNG
media_image1.png
1216
853
media_image1.png
Greyscale
Annotated fig. 13 of Baek
Regarding claim 24, Baek teaches the method [0134-0135, 0142, 0156] of claim 21. Baek also teaches further comprising forming the DCG transistor (210a-II) fig. 13 [0077] and the SF (210a-I) fig. 13 [0077] such that a distance (D) between (sidewalls of) the (source/drain 211 of) DCG transistor (210a-II) and the (gate 213 of) SF (210a-I) equals a width (W) of an isolation structure (comprising 214 with 216 with 242) fig. 13 [0081-0082, 0086] (see fig. 20 for 214, 216 labels) between the DCG transistor (210a-I) and the SF (210a-II) (see annotated fig. 13 above).
Regarding claim 25, Baek teaches the method [0134-0135, 0142, 0156] of claim 24. Baek also teaches wherein the distance (D) between the DCG transistor (210a-II) fig. 13 [0077] and the SF (210a-I) fig. 13 [0077] equals a distance (D) between a source region (211) fig. 13 [0082] of the DCG transistor (210a-I) and a gate electrode (213) fig. 13 [0082] (see fig. 20 for label) of the SF (210a-I) (as defined in annotated fig. 13 above).
Regarding claim 26, Baek teaches the method [0134-0135, 0142, 0156] of claim 25. Baek also teaches further comprising forming the DCG transistor (210a-II) fig. 13 [0077] and the SF (210a-I) fig. 13 [0077] with parallel orientations (210a’s have identical, vertically-oriented shapes).
Regarding claim 27, Baek teaches the method [0134-0135, 0142, 0156] of claim 21. Baek also teaches wherein bonding [see fig. 31, 0157] the first semiconductor substrate (102) fig. 13 [0121] to the second semiconductor substrate (202) fig. 13 [0121] forms a floating diffusion node (232, 234 are electrically connected to floating diffusion 110 through bonded 162/262) [0006-0008, 0084-0086] that includes a wiring structure (comprising 234 with right 232) fig. 13 [0086, 0092] having only a single lateral branch (horizontally-extending 234) in the second metal interconnect structure (comprising 234, 252, 266) and being otherwise vertically extending (right 232 vertically-extends [0086]) between (in the vertical space between) the floating diffusion region (110) and a gate electrode (213) fig. 13 [0096] of the source follower (210a-I) fig. 13 [0077] (as defined in annotated fig. 13 above).
Regarding claim 28, Baek teaches the method [0134-0135, 0142, 0156] of claim 21. Baek also teaches further comprising forming an array of lenses (134) fig. 13 [0095] positioned to focus light [0095] on groups of four (4 PX’s with corners facing each other) of the photosensitive areas (PX) fig. 4 [0057] (see fig. 4 for array of pixels [0057], each comprising an array of respective lens 134 [0094]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 22-23 and 30-35 are rejected under 35 U.S.C. 103 as being unpatentable over Baek (U.S. PG Pub No US2025/0151445A1) in view of Kim (U.S. PG Pub No US2022/0360731A1).
Regarding claim 22, Baek teaches the method [0134-0135, 0142, 0156] of claim 21. Baek also teaches further comprising connecting each DCG transistor (DCX) fig. 2 [0050] (corresponding to 210a-II [0077]) in series [see fig. 2, 0050] with a corresponding reset transistor (RX) fig. 2 [0050] (corresponding to 210b [0077]) and coupling each floating diffusion region (110) fig. 13 [0077] to a side (211) fig. 13 [0077-0078] of the corresponding DCG transistor (210a-II source/drain 211 connected to respective 110 by respective 162/262 interconnect structure [0157]).
However, Baek does not explicitly disclose coupling each floating diffusion region (110) fig. 13 [0077] to a source side (211) of the corresponding DCG transistor (210a-II) (teaches, for example, floating diffusion region 110 may be electrically connected to the drain terminal of DCG instead [0077 Baek]).
Kim teaches a method of making an image sensor [see title, 0060] comprising coupling (‘electrically connecting’ [0076]) each floating diffusion region (each FD2) fig. 3A [0118] to a source side (SDR2a) fig. 4 [0076] of the corresponding DCG transistor (DCX comprising DCG) fig. 4 [0075-0076].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the image sensor of Baek such that the floating diffusion region(s) of each pixel are, at least in part [0075-0076], explicitly electrically connected with each of the source regions of the corresponding DCG transistor [0075-0077] in order to improve electric characteristics [0002, 0005, 0166] of the image sensor by enhancing the integration density [0002, 0005, 0166] of electrical interconnections with transistor circuitry [0075-0077], as taught by Kim.
Regarding claim 23, Baek in view of Kim teaches the method [0134-0135, 0142, 0156] of claim 22. Baek in view of Kim also teaches further comprising:
forming a first contact plug (left 232) fig. 13 [0086, 0154] (see [fig. 29, 0154] for 232 formation) abutting the source side (source/drain 211) fig. 13 [0078] (respective source/drain 211 chosen to be source when modified by Kim) of the DCG transistor (210a-II) annotated fig. 13 [0077];
forming a second contact plug (right 232) fig. 13 [0086, 0154] (see [fig. 29, 0154] for 232 formation) abutting (see fig. 6, [0096] for close-up of abutting of 232/213) a gate electrode (213) fig. 13 [0078] of the SF (210a-I) annotated fig. 13 [0077];
forming a horizontal wire (234) fig. 29 [0154-0155] extending (horizontally) between the (tops of) first contact plug (left 232) and the second contact plug (right 232); and
forming a straight vertical column (SC) annotated fig. 13 above [0157] (SC having vertically-straight orientation/symmetry) of metal (comprising 152, 252, 162, 262) fig. 13 [0092, 0157] (formed of copper [0092, 0157]) extending between (in the vertical space between) the horizontal wire (234) and the floating diffusion region (110), the straight vertical column (SC) comprising first components (152, 166) in the first metal interconnect structure (comprising 152, 166) and second components (252, 266) in the second metal interconnect structure (comprising 152, 166).
Regarding claim 30, Baek teaches a method [0135, 0142, 0156] of making an image sensor (17) fig. 13 [0134], comprising:
receiving a first semiconductor substrate (102) fig. 15 [0136];
forming an photodetector (‘pixels’ / cells of APS) fig. 15 [0136] comprising a photosensitive area (108) fig. 15 [0136], a floating diffusion region (110) fig. 15 [0136], and a transfer gate (112) fig. 16 [0140, 0066-0068] in the first semiconductor substrate (102);
forming a first metal interconnect structure (comprising 150, 152, 154, 162 in 142) fig. 17 [0141, 0073] (152, 154, 162 may be formed of copper) [0073-0074] comprising a plurality of metallization layers (154) over a first (bottom) side of the first semiconductor substrate (102);
receiving a second semiconductor substrate (202) fig. 19 [0143];
forming source followers (SFs) (210a-I) fig. 13 [0077] (refer to annotated fig. 13 below for designation of SF), select gate transistors (210b serving as “selection transistor” – not explicitly shown) fig. 13 [0077], dual conversion gain transistors (DCG) transistors (210a-II) fig. 13 [0077] (refer to annotated fig. 13 below for designation of DCG), and reset transistors (210b) fig. 13 [0077] on (supported by) the second semiconductor substrate (202) (each of these pixel transistors included on second substrate 202 per pixel [0046, 0059]; refer to fig. 20 [0144] for transistor formation step),
forming a second metal interconnect structure (comprising 262 in 222) fig. 29 [0154] (262 formed of copper) [0157] comprising a plurality of metallization layers (262’s) over the second semiconductor substrate (202);
forming a wiring structure (WS) [see annotated fig. 13 below] with components in the first (152, 162) and second (262, 252, 234, 232) metal interconnect structures that couples [0006-0008, 0077-0078] the floating diffusion region (110) to a gate electrode (213) fig. 13 [0078] of the SF (210a-I) annotated fig. 13 [0077] (see fig. 6 for close-up) and to a region (211) fig. 13 [0078] of the DCG transistor (210a-II) annotated fig. 13 [0077]; and
bonding [see fig. 31, 0157] the first semiconductor substrate (102) to the second semiconductor substrate (202) via bonding (Cu-Cu bonding) [0157] between the first (comprising 162) and second (comprising 262) metal interconnect structures,
wherein the photosensitive area (108) and the floating diffusion region (110) are contained within a cell (see “cell” as defined in annotated fig. 13 below) of a grid (grid defined by 106’s) and the gate electrode (213), the source region (211), and the wiring structure (WS) are contained within a vertical extension of the cell (see annotated fig. 13 below).
[AltContent: arrow][AltContent: textbox (SC)][AltContent: rect][AltContent: arrow][AltContent: textbox (WS)][AltContent: rect][AltContent: connector][AltContent: connector][AltContent: arrow][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (One-to-one correspondence between FD’s 110 and SF’s 210a-I) )][AltContent: textbox (210a-II)][AltContent: textbox (210a-I)][AltContent: arrow][AltContent: textbox (Single-cell)]
PNG
media_image1.png
1216
853
media_image1.png
Greyscale
Annotated fig. 13 of Baek
However, Baek does not explicitly disclose forming a wiring structure (WS) [see annotated fig. 13 above] that couples the floating diffusion region (110) to a source region (211) fig. 13 [0078] of the DCG transistor (210a-II) annotated fig. 13 [0077] (teaches, for example, floating diffusion region 110 may be electrically connected to the drain terminal 211 of DCG instead [0077 Baek]).
Kim teaches a method of making an image sensor [see title, 0060] comprising forming a wiring structure (‘conductive line’; not shown) [0076] that couples the floating diffusion region (FD2) fig. 3A [0118] to a source region (SDR2a) fig. 4 [0076] of the DCG transistor (DCX comprising DCG) fig. 4 [0075-0076].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the image sensor of Baek such that the floating diffusion region(s) of each pixel are, at least in part [0075-0076], explicitly electrically connected with each of the source regions of the corresponding DCG transistor [0075-0077] in order to improve electric characteristics [0002, 0005, 0166] of the image sensor by enhancing the integration density [0002, 0005, 0166] of electrical interconnections with transistor circuitry [0075-0077], as taught by Kim.
Regarding claim 31, Baek teaches in view of Kim teaches the method [0134-0135, 0142, 0156] of claim 30. Baek also teaches further comprising connecting the reset transistor (RX) fig. 2 [0050] (corresponding to 210b [0077]) in series [see fig. 2, 0050] with the DCG transistor (DCX) fig. 2 [0050] (corresponding to 210a-II).
Further, Baek in view of Kim (with reference to Kim) teaches coupling the floating diffusion region (FD2) fig. 3A [0118] to the source region (SDR2a) fig. 4 [0076] of the DCG transistor (DCX comprising DCG) fig. 4 [0075-0076].
Regarding claim 32, Baek teaches the method [0134-0135, 0142, 0156] of claim 31. Baek also teaches wherein forming the wiring structure (WS) [see annotated fig. 13 above] comprises forming a first wire (234) fig. 13 [0085] in the second metal interconnect structure (comprising 266, 252, 234) that couples the source region (source/drain 211) fig. 13 [0078] of the DCG transistor (210a-II) fig. 13 [0077] to the gate electrode (213) fig. 13 [0078] of the source follower (210a-I) fig. 13 [0077] and aligning the (bottom, left corner of) floating diffusion region (110) directly opposite the (top, right corner of) first wire (234) during bonding [see fig. 31, 0157].
Regarding claim 33, Baek teaches in view of Kim teaches the method [0134-0135, 0142, 0156] of claim 32. Baek also teaches wherein forming the wiring structure (WS) further comprises forming a straight vertical column (SC) annotated fig. 13 above [0157] (SC having vertically-straight orientation/symmetry) of metal (comprising 152, 252, 162, 262) fig. 13 [0092, 0157] (formed of copper [0092, 0157]) connecting [0006-0008, 0077] the floating diffusion region (110) fig. 13 [0077] to the first wire (234) fig. 13 [0085].
Regarding claim 34, Baek teaches in view of Kim teaches the method [0134-0135, 0142, 0156] of claim 30. Baek also teaches wherein forming the floating diffusion region (110) fig. 13 [0077] comprises forming the floating diffusion region (110) in a corner (corner of 102, defined by border with 110, being oppositely doped from each other) [0138] of the cell (‘cell’ comprising 102, see annotated fig. 13 above).
Regarding claim 35, Baek teaches in view of Kim teaches the method [0134-0135, 0142, 0156] of claim 30. Baek also teaches wherein forming an isolation structure (106) fig. 15 [0137] comprises extending the isolation structure (106) from the first side (bottom of 102) fig. 15 [0136] to a second side (top of 102) fig. 15 [0136] of the first semiconductor substrate (102).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (U.S. PG Pub No US2025/0151445A1), as applied in claim 28 above, in view of Chen (U.S. PG Pub No US2021/0337147A1).
Regarding claim 29, Baek teaches the method [0134-0135, 0142, 0156] of claim 28. However, Baek does not explicitly disclose further comprising configuring two of the four photosensitive areas as image sensing pixels and two of the four photosensitive areas as phase detection autofocus pixels (phase detection autofocus pixels not disclosed).
Chen teaches a method [0011] of forming an image sensor (202) fig. 2 [0023] further comprising configuring two of the four photosensitive areas (four pixels of 204A) fig. 2 [0024] as image sensing pixels (G) fig. 2 [0026] and two of the four photosensitive areas as phase detection autofocus pixels (PD) fig. 2 [0026].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the pixel array of Baek’s image sensor such that at least some of the pixels are made to serve as phase detection autofocus pixels (PDAF’s) [0020, 0026] in order to enhance the functionality [0002] of the image sensor by providing the capacity for autofocusing operations [0016-0017], as taught by Chen.
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Baek (U.S. PG Pub No US2025/0151445A1) modified by Kim (U.S. PG Pub No US2022/0360731A1), as applied in claim 30 above, in view of Anderson (U.S. PG Pub No US2012/0181588A1).
Regarding claim 36, Baek in view of Kim teaches the method [0134-0135, 0142, 0156] of claim 30. Baek also teaches wherein forming the transfer gate (112) fig. 16 [0140, 0066-0068] and the floating diffusion region (110) fig. 15 [0136] comprises forming the floating diffusion region (110) on (supported by) a source side (side nearer PD) [0070] of the transfer gate (112).
However, Baek does not explicitly disclose and forming a drain side of the transfer gate (112) wider than the source side.
Anderson teaches a method [0008] of forming an image sensor (64) fig. 6 [0031] comprising forming a drain side (right sidewall of 40 further from 54) fig. 6 [0041] of the transfer gate (40 of 60) fig. 6 [0041] wider (vertical-width of right sidewall of 40 greater than vertical width of left sidewall of 40) than the source side (left sidewall of 40 nearer to 54) fig. 6 [0041].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the gate of the transfer transistor of Baek to have an asymmetric geometry [0041] with the drain side being wider in the vertical direction that the source side [0041] in order to introduce threshold voltage asymmetry [0041, 0056] to the gate electrode which improves the efficiency of charge transfer by the transfer transistor [0041] so as to reduce lag and noise of the pixel cell [0041], as taught by Anderson.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are all considered relevant to the present disclosure because they each feature examples of image sensors with first substrates having floating diffusion regions connected by interconnect structures to second substrates hosting transistor circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 04/18/2026
Prosecution Insights