DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 20 and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20150029683 A1; hereinafter Kim) in view of Lai et al. (US 20200211477 A1; hereinafter Lai).
Regarding claim 20, FIGS. 1-2 of Kim teach a display panel (1000 ¶ [0028]) including a folding area (BA) that is folded with respect to a virtual axis (AX) and a non-folding area (NA) that is not folded with respect to the virtual axis (AX ¶ [0030]), the display panel (1000) comprising a plurality of pixels in the folding area (BP) and the non-folding area (NP ¶ [0036]).
Kim does not teach the display panel comprising: a driving element layer comprising a transistor; and the light emitting element layer comprising: a first electrode, a plurality of emission layers disposed on the first electrode, and a plurality of second electrodes disposed on the emission layers, wherein: at least one of the plurality of second electrodes is electrically connected to the transistor, the first electrode comprises: a plurality of first sub electrodes overlapping the plurality of emission layers, and a connection pattern layer that electrically connects the plurality of first sub electrodes to each other, and a density of the connection pattern layer in the folding area and a density of the connection pattern layer in the non-folding area are different from each other.
FIGS. 26, 29, and 33 of Lai teach a display panel comprising: a driving element layer (driving layer including transistor T1) comprising a transistor (T1 ¶ [0174]); and a light emitting element layer (light-emitting element layer including 200 ¶ [0174]) comprising: a first electrode (201, 108, 106 ¶ [0174],[0304]), a plurality of emission layers (202) disposed on the first electrode (201), and a plurality of second electrodes (203) disposed on the emission layers (202 ¶ [0174]), wherein: at least one of the plurality of second electrodes (203) is electrically connected to the transistor (203 electrically connected to driving signal via 225, 109 and/or to T1 via 108, 106, 102 ¶ [0111],[0326]), the first electrode (201, 108, 106) comprises: a plurality of first sub electrodes (104) overlapping the plurality of emission layers (202 ¶ [0309]), and a connection pattern layer (105) that electrically connects the plurality of first sub electrodes (104 ¶ [0308]) to each other, and a density of the connection pattern layer (density of 105) in a central area of the display panel (central area of display panel shown in FIG. 33) and a density of the connection pattern layer (density of 105) in an outer area (outer area of display panel shown in FIG. 33) are different from each other.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel taught by Kim with the display panel taught by Lai for the purpose of ensuring high light brightness and high light efficiency (¶ [0302]).
Thus, Kim in view of Lai teaches the density of the connection pattern layer (density of 105 of Lai) in the folding area (BA of Kim) and the density of the connection pattern layer (density of 105 of Lai) in the non-folding area (NA of Kim) are different from each other.
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Regarding claim 27, FIGS. 1-2 of Kim teach a display panel (1000 ¶ [0028]) including a folding area (BA) that is folded with respect to a virtual axis (AX) and a non-folding area (NA) that is not folded with respect to the virtual axis (AX ¶ [0030]), the display panel (1000) comprising a plurality of pixels in the folding area (BP) and the non-folding area (NP ¶ [0036]).
Kim does not teach the display panel comprising: a driving element layer comprising a transistor; and a light emitting element layer comprising: a first electrode, a plurality of emission layers disposed on the first electrode, and a plurality of second electrodes disposed on the emission layers, wherein: each of the plurality of second electrodes is electrically connected to the transistor, the first electrode comprises: a plurality of first sub electrodes overlapping the plurality of emission layers, and a connection pattern layer that electrically connects the first sub electrodes to each other, the connection pattern layer comprises: a plurality of first sub connection parts having a multilayer structure; and a plurality of second sub connection parts having a single-layer structure, the plurality of first sub connection parts are disposed in the non-folding area, and the plurality of second sub connection parts are disposed in the folding area.
FIGS. 26, 29, and 33 of Lai teach a display panel comprising: a driving element layer (driving layer including transistor T1) comprising a transistor (T1 ¶ [0174]); and a light emitting element layer (light-emitting element layer including 200 ¶ [0174]) comprising: a first electrode (201, 108, 106, 102s ¶ [0174],[0304], [0307],[0310]), a plurality of emission layers (202) disposed on the first electrode (202 on 201, 108, 106, 102s), and a plurality of second electrodes (203) disposed on the emission layers (202 ¶ [0174]), wherein: each of the plurality of second electrodes (203) is electrically connected to the transistor (203 electrically connected to driving signal via 225, 109 and/or to T1 via 108, 106, 102 ¶ [0111],[0326]), the first electrode (201, 108, 106, 102s) comprises: a plurality of first sub electrodes (104) overlapping the plurality of emission layers (202 ¶ [0309]), and a connection pattern layer (105, 102s) that electrically connects the first sub electrodes (104 ¶ [0308]) to each other, the connection pattern layer (105, 102s) comprises: a plurality of first sub connection parts (102s) having a multilayer structure (multilayer structure of 102s ¶ [0310]); and a plurality of second sub connection parts (105) having a single-layer structure (single-layer structure of 105 ¶ [0308]), the plurality of first sub connection parts (102s).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel taught by Kim with the display panel taught by Lai for the purpose of ensuring high light brightness and high light efficiency (¶ [0302]).
Thus, Kim in view of Lai teaches the plurality of first sub connection parts (102s of Lai) are disposed in the non-folding area (NA of Kim), and the plurality of second sub connection parts (105 of Lai) are disposed in the folding area (BA of Kim).
Regarding claim 28, Kim as modified teaches the display panel of claim 27, and FIGS. 26 and 29 of Lai further teach wherein: each of the plurality of first sub connection parts (102s) comprises: a first conductive layer (bottom instance of 104 in 102s); a metal layer (105 in 102s) disposed on the first conductive layer (bottommost instance of 104 in 102s); and a second conductive layer (top instance of 104 in 102s) disposed on the metal layer (105 in 102s), and each of the plurality of second sub connection parts (105 in 106) comprises the metal layer (¶ [0308],[0310]).
Allowable Subject Matter
Claims 1-19 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites a display panel comprising: a base layer bendable with respect to a virtual axis; a driving element layer comprising a transistor; and a light emitting element layer comprising: a first electrode, a plurality of emission layers disposed on the first electrode, and a plurality of second electrodes disposed on the emission layers, wherein: at least one of the plurality of second electrodes is electrically connected to the transistor, the first electrode comprises: a plurality of first sub electrodes overlapping the plurality of emission layers, and a connection pattern layer that electrically connects the first sub electrodes to each other, the connection pattern layer comprises: a first connection pattern layer that electrically connects the plurality of first sub electrodes to each other in a first direction parallel to the virtual axis; and a second connection pattern layer that electrically connects the plurality of first sub electrodes to each other in a second direction intersecting the first direction, and a density of the first connection pattern layer is greater than a density of the second connection pattern layer.
FIGS. 1-2 of Kim teach a display panel (1000 ¶ [0028]) including a folding area (BA) that is folded with respect to a virtual axis (AX) and a non-folding area (NA) that is not folded with respect to the virtual axis (AX ¶ [0030]), the display panel (1000) comprising a plurality of pixels in the folding area (BP) and the non-folding area (NP ¶ [0036]).
FIGS. 26, 29, and 33 of Lai teach a display panel comprising: a driving element layer (driving layer including transistor T1) comprising a transistor (T1 ¶ [0174]); and a light emitting element layer (light-emitting element layer including 200 ¶ [0174]) comprising: a first electrode (201, 108, 106 ¶ [0174],[0304]), a plurality of emission layers (202) disposed on the first electrode (201), and a plurality of second electrodes (203) disposed on the emission layers (202 ¶ [0174]), wherein: at least one of the plurality of second electrodes (203) is electrically connected to the transistor (203 electrically connected to driving signal via 225, 109 and/or to T1 via 108, 106, 102 ¶ [0111],[0326]), the first electrode (201, 108, 106) comprises: a plurality of first sub electrodes (104) overlapping the plurality of emission layers (202 ¶ [0309]), and a connection pattern layer (105) that electrically connects the plurality of first sub electrodes (104 ¶ [0308]) to each other, and a density of the connection pattern layer (density of 105) in a central area of the display panel (central area of display panel shown in FIG. 33) and a density of the connection pattern layer (density of 105) in an outer area (outer area of display panel shown in FIG. 33) are different from each other.
Thus, Kim in view of Lai teaches the density of the connection pattern layer (density of 105 of Lai) in the folding area (BA of Kim) and the density of the connection pattern layer (density of 105 of Lai) in the non-folding area (NA of Kim) are different from each other.
However, the prior art fails to teach or reasonably suggest “a density of the first connection pattern layer is greater than a density of the second connection pattern layer” together with all the limitations of claim 1 as claimed. Claims 2-19 are allowable insofar as they depend upon and require all the limitations of claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 21-26 and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 21 recites the display panel of claim 20, wherein the density of the connection pattern layer in the folding area gradually decreases as being closer to the virtual axis.
Kim in view of Lai teaches the display panel of claim 20.
However, the prior art fails to teach or reasonably suggest “wherein the density of the connection pattern layer in the folding area gradually decreases as being closer to the virtual axis” together with all the limitations of claims 21 and 20 as claimed.
Claim 22 recites the display panel of claim 20, wherein the connection pattern layer comprises: a plurality of first connection parts that electrically connect the first sub electrodes, which are adjacent to each other in a first direction parallel to the virtual axis, to each other; and a plurality of second connection parts that electrically connect the first sub electrodes, which are adjacent to each other in a second direction intersecting the first direction, to each other.
Kim in view of Lai teaches the display panel of claim 20.
However, the prior art fails to teach or reasonably suggest “wherein the connection pattern layer comprises: a plurality of first connection parts that electrically connect the first sub electrodes, which are adjacent to each other in a first direction parallel to the virtual axis, to each other; and a plurality of second connection parts that electrically connect the first sub electrodes, which are adjacent to each other in a second direction intersecting the first direction, to each other” together with all the limitations of claims 22 and 20 as claimed. Claims 23-26 contain allowable subject matter insofar as they depend upon and require all the limitations of claims 22 and 20.
Claim 29 recites the display panel of claim 27, wherein a number of the plurality of second sub connection parts disposed in a direction parallel to the virtual axis gradually increases as being closer to the virtual axis.
Kim in view of Lai teaches the display panel of claim 27.
However, the prior art fails to teach or reasonably suggest “wherein a number of the plurality of second sub connection parts disposed in a direction parallel to the virtual axis gradually increases as being closer to the virtual axis” together with all the limitations of claims 27 and 29 as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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