Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/26/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-11, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 20190148476 A1). Note: Park (US 20140322067 A1, hereinafter Park ‘067) is relied upon as an extra reference to show an inherent characteristic of Park. MPEP 2131.01 (III).
Regarding claim 1, Park discloses a display panel (Fig. 1) comprising:
a display area (DA); a circuit element layer (Fig. 10: See dashed reference lines in annotated figure) comprising insulating layers (111/112/113/114/115) and a transistor (T6) in the display area,
a first insulating layer (114) among the insulating layers defining a first through hole (See annotated figure) of the circuit element layer which is in the display area;
a light emitting element (OLED) electrically connected to the transistor (connected by at least 155; connection schematic is also shown in Fig. 3); and
an anti-shock pattern (140. Note: anti-shock is interpreted here consistent with Applicant’s disclosure: [0027] which describes this pattern reducing stress in the panel. Park describes pattern 140 in a similar way in [0132]: “stress”.) having an elastic modulus greater than about 100 gigapascals ([0100]: “titanium”. See below for additional remarks regarding the elastic modulus), the anti-shock pattern being in the first through hole.
Illustrated below is a marked and annotated figure of Fig. 10 of Park.
PNG
media_image1.png
506
606
media_image1.png
Greyscale
Regarding the “elastic modulus”, Park teaches the anti-shock pattern includes titanium ([0100]: “titanium”) but does not disclose the characteristic claimed: “elastic modulus”. However, the claimed characteristic “an elastic modulus greater than about 100” is an inherent characteristic of titanium. Park ‘067 teaches titanium having an elastic modulus greater than about 100 gigapascals (Fig. 9, a table: Ti has an elastic modulus of 102.7 gigapascals), and this reference is relied upon here consistent with the guidance of MPEP 2112 (III) Inherency and MPEP 2131.01 (III) Extra Reference. Therefore, Park ‘067 teaches Park anticipates the claimed anti-shock pattern.
Regarding claim 2, Park discloses the display panel of claim 1 (Fig. 10), wherein the anti-shock pattern comprises a metal material ([0100]: “titanium”).
Regarding claim 3, Park discloses the display panel of claim 1 (Fig. 10), wherein the first insulating layer which defines the first through hole comprises an inorganic material ([0130]: “inorganic material”).
Regarding claim 4, Park discloses the display panel of claim 1 (Fig. 10), wherein the transistor comprises: a semiconductor pattern ([0115]: “semiconductor layer”) comprising a source (S6), a channel (A6) and a drain (D6); and a gate electrode (G6) on the semiconductor pattern, and the anti-shock pattern does not overlap the source and the drain of the transistor (pattern 140 does not overlap any part of transistor T6 in the vertical or horizontal direction. See annotated figure for direction designation).
Regarding claim 5, Park discloses the display panel of claim 1 (Fig. 10), wherein the circuit element layer further comprises a connection electrode (See annotated figure) electrically connecting the transistor and the light emitting element to each other (connection schematic is also shown in Fig. 3), and the anti-shock pattern is on a same layer as the connection electrode (these structures have at least some horizontal overlap, and thus are “on a same level”).
Regarding claim 6, Park discloses the display panel of claim 5 (Fig. 10), wherein the anti-shock pattern comprises a same material as the connection electrode ([0100]: “the first connection wiring 140 and the second connection wiring 150 may have a titanium/aluminum/titanium (Ti/Al/Ti) stacked structure”).
Regarding claim 9, Park discloses the display panel of claim 1 (Fig. 10), wherein the circuit element layer further comprises: a second insulating layer (113) among the insulating layers which defines a second through hole (See annotated figure) of the circuit element layer which is in the display area; and a shock absorption pattern (161; [0096]: “reduce an influence of an external impact”) penetrating the second through hole, the shock absorption pattern comprising an organic material ([0096]: “organic material layer”).
Regarding claim 10, Park discloses the display panel of claim 9 (Fig. 10), wherein within the circuit element layer, the shock absorption pattern surrounds (horizontally surrounds) the transistor and the anti-shock pattern (Fig. 4 shows top-down view where 161 horizontally surrounds the cited portions of these structures).
Regarding claim 11, Park discloses the display panel of claim 9 (Fig. 10), wherein an elastic modulus of the shock absorption pattern in the second through hole is lower ([0096]: “the hardness of the inorganic insulating layer is higher than that of the organic material layer 161”) than the elastic modulus of the anti-shock pattern in the first through hole.
Regarding independent claim 19, Park discloses a display panel (Fig. 1) comprising:
a display area (DA);
a plurality of pixels (PX; [0050]: “Pixels”) in the display area,
each of the pixels comprising a pixel driving circuit ([0014]: “a driving thin film transistor”) and a light emitting element ([0050]: “an organic light-emitting diode (OLED)”) which is electrically connected to the pixel driving circuit (Fig. 3 is a schematic showing the electrical connections of the driving circuit);
a planar area of the display area (Fig. 10: horizontal plane, See annotated figure for direction designation) including the pixel driving circuit (T6 is included within this area); and
a plurality of metal anti-shock patterns (140. Note: anti-shock is interpreted here consistent with Applicant’s disclosure: [0027] which describes this pattern reducing stress in the panel. Park describes pattern 140 in a similar way in [0132]: “stress”.) within the planar area of the display area,
each of the metal anti-shock patterns having an elastic modulus equal to or greater than about 100 gigapascals ([0100]: “titanium”. See below for additional remarks regarding the elastic modulus).
Regarding the “elastic modulus”, Park teaches the anti-shock pattern includes titanium ([0100]: “titanium”) but does not disclose the characteristic claimed: “elastic modulus”. However, the claimed characteristic “an elastic modulus greater than about 100” is an inherent characteristic of titanium. Park ‘067 teaches titanium having an elastic modulus greater than about 100 gigapascals (Fig. 9, a table: Ti has an elastic modulus of 102.7 gigapascals), and this reference is relied upon here consistent with the guidance of MPEP 2112 (III) Inherency and MPEP 2131.01 (III) Extra Reference. Therefore, Park ‘067 teaches Park anticipates the claimed anti-shock pattern.
Regarding claim 20, Park discloses the display panel of claim 19 (Fig. 10), further comprising an organic shock absorption pattern (161; [0096]: “organic material layer…reduce an influence of an external impact”) in the display area and having an elastic modulus lower ([0096]: “the hardness of the inorganic insulating layer is higher than that of the organic material layer 161”) than the elastic modulus of the anti-shock pattern, the organic shock absorption pattern surrounding (horizontally surrounds) the planar area of the display area which includes the pixel driving circuit (Fig. 4 shows top-down view where 161 horizontally surrounds the cited portions of these structures).
Claims 1, 7-8, and 12-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han (US 20210375950 A1). Note: Park (US 20140322067 A1, hereinafter Park ‘067) is relied upon as an extra reference to show an inherent characteristic of Han. MPEP 2131.01 (III).
Regarding claim 1, Han discloses a display panel comprising (Fig. 2):
a display area (DA);
a circuit element layer (Fig. 4: See dashed reference lines in annotated figure) comprising insulating layers (at least 105/107; [0106]: “insulating layer”; [0108]: “insulating layer”) and a transistor (TFT2) in the display area,
a first insulating layer (105) among the insulating layers defining a first through hole (See annotated figure) of the circuit element layer which is in the display area;
a light emitting element (OLED; [0099]: “organic light-emitting diode”) electrically connected to the transistor (connected by at least CM; connection schematic is also shown in Fig. 3); and
an anti-shock pattern (137b. Note: anti-shock is interpreted here consistent with Applicant’s disclosure: Fig. 6B: pattern CP, which is illustrated as a wiring and via) having an elastic modulus greater than about 100 gigapascals ([0130]: “titanium”. See below for additional remarks regarding the elastic modulus), the anti-shock pattern being in the first through hole.
Regarding the “elastic modulus”, Han teaches the anti-shock pattern includes titanium ([0130]: “titanium”) but does not disclose the characteristic claimed: “elastic modulus”. However, the claimed characteristic “an elastic modulus greater than about 100” is an inherent characteristic of titanium. Park ‘067 teaches titanium having an elastic modulus greater than about 100 gigapascals (Fig. 9, a table: Ti has an elastic modulus of 102.7 gigapascals), and this reference is relied upon here consistent with the guidance of MPEP 2112 (III) Inherency and MPEP 2131.01 (III) Extra Reference. Therefore, Park ‘067 teaches Han anticipates the claimed anti-shock pattern.
Regarding claim 7, Han discloses the display panel of claim 1 (Fig. 3),
wherein the circuit element layer further comprises sub-scan lines (SL1/SL2/Sn-1/Sn+1. [0099] teaches the configuration of Fig. 4: TFT2 corresponds to Fig. 3: T1, thus, the sub-scan line Fig. 3: SL1 corresponds to Fig. 4: 136b. [0099] teaches the configuration of Fig. 4: TFT1 corresponds to Fig. 3: T3/T4/T7, thus, the sub-scan lines Fig. 3: SL2/Sn-1/Sn+1 corresponds to Fig. 4: 136a.) which are on different layers from each other (136a and 136b are on different layers in the Z direction),
overlap each other (these lines are configured in the same display, thus they must overlap in at least some direction), and
receive a same electrical signal (each are configured to receive a scan signal, thus “a same electrical signal”; [0075]: “scan signal”).
Regarding claim 8, Han discloses the display panel of claim 7 (Fig. 4), wherein the anti-shock pattern overlaps the sub-scan lines (the pattern and these lines are configured in the same display, thus they must overlap in at least some direction).
Regarding independent claim 12, Han discloses a display panel (Fig. 4) comprising:
a base substrate (100); in order from the base substrate:
a first semiconductor pattern layer (134b; [0104]: “a silicon semiconductor material”);
a first insulating layer (105; [0106]: “insulating layer”);
a first conductive pattern layer (144; [0109]: “electrode”);
a second insulating layer (107; [0108]: “insulating layer”);
a second conductive pattern layer (146; [0111]: “electrode”);
a third insulating layer (109; [0112]: “insulating layer”); and
a light emitting element (OLED; [0099]: “organic light-emitting diode”),
wherein at least one insulating layer among the first, second and third insulating layers defines a first through hole (See annotated figure); and
an anti-shock pattern (137b. Note: anti-shock is interpreted here consistent with Applicant’s disclosure: Fig. 6B: pattern CP, which is illustrated as a wiring and via) having an elastic modulus equal to or greater than about 100 gigapascals ([0130]: “titanium”. See below for additional remarks regarding the elastic modulus), the anti-shock pattern in the first through hole.
Illustrated below is a marked and annotated figure of Fig. 4 of Han.
PNG
media_image2.png
609
556
media_image2.png
Greyscale
Regarding the “elastic modulus”, Han teaches the anti-shock pattern includes titanium ([0130]: “titanium”) but does not disclose the characteristic claimed: “elastic modulus”. However, the claimed characteristic “an elastic modulus greater than about 100” is an inherent characteristic of titanium. Park ‘067 teaches titanium having an elastic modulus greater than about 100 gigapascals (Fig. 9, a table: Ti has an elastic modulus of 102.7 gigapascals), and this reference is relied upon here consistent with the guidance of MPEP 2112 (III) Inherency and MPEP 2131.01 (III) Extra Reference. Therefore, Park ‘067 teaches Han anticipates the claimed anti-shock pattern.
Regarding claim 13, Han discloses the display panel of claim 12 (Fig. 4), wherein the first semiconductor pattern layer comprises a first semiconductor pattern of a first transistor (TFT2; [0099]: “thin-film transistor”), connected to the light emitting element (connected at least by 138b; connection schematic is also shown in Fig. 3), and the first conductive pattern layer comprises a first gate electrode ([0103]: “gate electrode”) of the first transistor, the first gate electrode overlapping the first semiconductor pattern (overlapping in the Z direction).
Regarding claim 14, Han discloses the display panel of claim 12 (Fig. 4), wherein the first to third insulating layers comprise an inorganic material (105 is [0106]: “inorganic insulating material”; 107 is [0108]: “inorganic insulating material”; 109 is [0112]: “inorganic insulating material”).
Regarding claim 15, Han discloses the display panel of claim 12 (Fig. 4), further comprising between the third insulating layer and the light emitting element, in order from the third insulating layer:
a second semiconductor pattern layer (134a; [0116]: “semiconductor layer”);
a fourth insulating layer (111; [0127]: “insulating layer”);
a third conductive pattern layer (136a; [0128]: “electrode”);
a fifth insulating layer (113; [0129]: “insulating layer”); and
a fourth conductive pattern layer (the layer includes a collection of patterns 137a/138a/137b/138b),
wherein at least one insulating layer among the first, second, third, fourth and fifth insulating layers (at least the first insulating layer 105) defines the first through hole in which the anti-shock pattern is disposed.
Regarding claim 16, Han discloses the display panel of claim 15 (Fig. 4), wherein the first semiconductor pattern layer (134b; [0104]: “a silicon semiconductor material”) and the second semiconductor pattern layer (134a; [0116]: “ITZO (InSnZnO), IGZO (InGaZnO), or the like”) comprise different semiconductor materials from each other (the cited materials are different compositions).
Regarding claim 17, Han discloses the display panel of claim 15 (Fig. 4), wherein the fifth insulating layer defines the first through hole (partially defines), and the anti-shock pattern is on a same layer as the fourth conductive pattern layer (pattern 137b in included in the cited collection defining the layer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Han as applied to claim 15 above, and further in view of Park.
Regarding claim 18, Han discloses the display panel of claim 15 (Fig. 4), but fails to teach it further comprising
“a shock absorption pattern comprising an organic material and having an elastic modulus lower than the elastic modulus of the anti-shock pattern,
wherein at least one insulating layer among the first to fifth insulating layers defines a second through hole, and
the shock absorption pattern penetrates the second through hole”.
Park discloses a display panel (Fig. 10) further comprising
a shock absorption pattern (161; [0096]: “reduce an influence of an external impact”) comprising an organic material ([0096]: “organic material layer”) and having an elastic modulus lower ([0096]: “the hardness of the inorganic insulating layer is higher than that of the organic material layer 161”) than the elastic modulus of the anti-shock pattern ([0100]: “the first connection wiring 140 and the second connection wiring 150 may have a titanium/aluminum/titanium (Ti/Al/Ti) stacked structure”),
wherein at least one insulating layer (113) among the first to fifth insulating layers (111/112/113/114/115) defines a second through hole (See annotated figure), and
the shock absorption pattern penetrates the second through hole (vertically penetrates, See annotated figure for direction designation).
Modifying the display panel of Han by including the shock absorption pattern of Park would arrive at the claimed panel configuration. Park teaches motivation for one of ordinary skill in the art before the effective filing date to include the shock absorption pattern in that it would protect the panel from damage ([0097]: “a probability that a crack propagates is low”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed shock absorption pattern configuration because it would protect the panel from damage. MPEP 2143 (I)(G).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
Prosecution Insights