DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 9-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2025/0098244) in view of Boselli (US 2009/0267154).
Regarding claim 1, Chang discloses, in at least figure 2 and related text, an electrostatic discharge protection device (100A, [16]), comprising:
a P-type semiconductor substrate (101, [21]);
an N-type deep well region located (102, [21]) in the P-type semiconductor substrate (101, [21]);
a first high-voltage P-type well region (134, [26]) located on the N-type deep well region (102, [21]);
a first high-voltage N-type well region (133, [24]) located on the N-type deep well region (102, [21]), wherein the first high-voltage N-type well region (133, [24]) and the first high-voltage P-type well region (134, [26]) are arranged side-by-side;
a second high-voltage P-type well region (132, [23]) located on the N-type deep well region (102, [21]), wherein the second high-voltage P-type well region (132, [23]) and the first high-voltage N-type well region (133, [24]) are arranged side-by-side;
a second high-voltage N-type well region (131, [22]) located on the N-type deep well region (102, [21]), wherein the second high-voltage N-type well region (131, [22]) and the second high-voltage P-type well region (132, [23]) are arranged side-by-side;
a first P-type doped region (114, [26]);
a second P-type doped region (112, [23]) located on the second high-voltage P-type well region (132, [23]);
a first N-type doped region (111, [22]) located on the second high-voltage N-type well region (131, [22]); and
a gate structure (113, [16]) disposed on the first high-voltage P-type well region (134, [26]), the first high-voltage N-type well region (133, [24]) and the second high-voltage P-type well region (132, [23]), wherein the gate structure (113, [16]) is located between the first P-type doped region (114, [26]) and the second P-type well region (132, [23]),
wherein the first P-type doped region (114, [26]) is electrically connected to a first voltage source (LN2, [30]),
wherein the gate structure (113, [16]), the second P-type doped region (112, [23]) and the first N-type doped region (111, [22]) are electrically connected to a second voltage source (LN1, [30]).
Chang does not explicitly disclose a low-voltage N-type well region located on the first high-voltage P-type well region; a first P-type doped region located on the low-voltage N-type well region.
Boselli teaches, in at least figure 2 and related text, the device comprising a low-voltage N-type well region (37, [32]) located on the first high-voltage P-type well region (38, [32]); a first P-type doped region (36, [32]) located on the low-voltage N-type well region (37, [32]), for the purpose of providing ESD protection for integrated circuits utilizing NMOS transistors including drain-extended MOS transistors ([46]).
Chang and Boselli are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang with the specified features of Boselli because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Chang to have the low-voltage N-type well region located on the first high-voltage P-type well region; the first P-type doped region located on the low-voltage N-type well region, as taught by Boselli, for the purpose of providing ESD protection for integrated circuits utilizing NMOS transistors including drain-extended MOS transistors ([46], Boselli).
Regarding claim 2, Chang in view of Boselli discloses the electrostatic discharge protection device as claimed in claim 1 as described above.
Chang does not explicitly disclose the low-voltage N-type well region completely overlaps the first P-type doped region.
Boselli teaches, in at least figure 2 and related text, the device comprising the low-voltage N-type well region (37, [32]) completely overlaps the first P-type doped region (36, [32]), for the purpose of providing ESD structure of vertical pnp bipolar transistor comprising p-emitter/cathode ([32]).
Chang and Boselli are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang with the specified features of Boselli because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Chang to have the low-voltage N-type well region completely overlaps the first P-type doped region, as taught by Boselli, for the purpose of providing ESD structure of vertical pnp bipolar transistor comprising p-emitter/cathode ([32], Boselli).
Regarding claim 3, Chang in view of Boselli discloses the electrostatic discharge protection device as claimed in claim 2 as described above.
Boselli further teaches, in at least figure 2 and related text, the low-voltage N-type well region (37, [32]) separates a bottom surface of the first P-type doped region (36, [32]) from the first high-voltage P-type well region (38, [32]), for the purpose of providing ESD structure of vertical pnp bipolar transistor comprising p-emitter/cathode ([32]).
Regarding claim 5, Chang in view of Boselli discloses the electrostatic discharge protection device as claimed in claim 1 as described above.
Chang does not explicitly disclose the low-voltage N-type well region partially overlaps the first P-type doped region.
Boselli teaches, in at least figure 2 and related text, the device comprising the low-voltage N-type well region (37, [32]) partially overlaps the first P-type doped region (36, [32]), for the purpose of providing ESD structure of vertical pnp bipolar transistor comprising p-emitter/cathode ([32]).
Chang and Boselli are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang with the specified features of Boselli because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Chang to have the low-voltage N-type well region partially overlaps the first P-type doped region, as taught by Boselli, for the purpose of providing ESD structure of vertical pnp bipolar transistor comprising p-emitter/cathode ([32], Boselli).
Regarding claim 9, Chang in view of Boselli discloses the electrostatic discharge protection device as claimed in claim 1 as described above.
Chang further discloses, in at least figure 2 and related text, a first isolation feature (124, [16]) disposed in the first high-voltage P-type well region (134, [26]) and close to a first interface between the first high-voltage P-type well region (134, [26]) and the first high-voltage N-type well region (133, [24]); and
a second isolation feature (123, [16]) disposed in the second high-voltage P-type well region (132, [23]) and close to a second interface between the second high-voltage P-type well region (132, [23]) and the first high-voltage N-type well region (133, [24]).
Regarding claim 10, Chang in view of Boselli discloses the electrostatic discharge protection device as claimed in claim 9 as described above.
Chang further discloses, in at least figure 2 and related text, the first high-voltage N-type well region (133, [24]) is located between and separated from the first isolation feature (124, [16]) and the second isolation feature (123, [16]) along a first direction that is substantially parallel to a top surface of the P-type semiconductor substrate (101, [21]).
Regarding claim 11, Chang in view of Boselli discloses the electrostatic discharge protection device as claimed in claim 9 as described above.
Chang further discloses, in at least figure 2 and related text, the gate structure (113, [16]) covers a portion of the first isolation feature (124, [16]) and a portion of the second isolation feature (123, [16]).
Regarding claim 13, Chang in view of Boselli discloses the electrostatic discharge protection device as claimed in claim 9 as described above.
Chang further discloses, in at least figure 2 and related text, a third isolation feature (122, [16]) disposed between the second high-voltage P-type well region (132, [23]) and the second high-voltage N-type well region (131, [22]), wherein opposite side surfaces of the third isolation feature are respectively adjacent to the second P-type doped region (112, [23]) and the first N-type doped region (111, [22]).
Allowable Subject Matter
Claims 4 and 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 2, and 4 that recite "a side surface of the low-voltage N-type well region away from the first high-voltage N-type well region is aligned with a boundary of the first high-voltage P-type well region away from the first N-type high-voltage well region" in combination with other elements of the base claims 1, 2, and 4.
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 9, and 12 that recite "a first side surface of the first isolation feature away from the first interface is adjacent to the low-voltage N-type well region and the first P-type doped region" in combination with other elements of the base claims 1, 9, and 12.
Claims 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 9, and 14 that recite "a first distance between the first silicide feature and the gate structure is greater than a second distance between the first P-type doped region and the gate structure" in combination with other elements of the base claims 1, 9, and 14.
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 19 that recite "the low-voltage N-type well region, the first high-voltage P-type well region and the N-type deep well region form a second parasitic bipolar junction transistor" in combination with other elements of the base claims 1 and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811