Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claims 1-20 are presented for examination. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2 and 4 -5 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ryu (US Pub. No. 2021/0202610 A1) . As to claim 1, Ryu discloses a display device ( 100, [0034] ) comprising: a pixel circuit layer (111 with TFT) comprising a base layer (111) and a pixel circuit (TFT) on the base layer (111) ; and a light emitting element (130 including electrodes 120/140) on the pixel circuit layer (111) , wherein the light emitting element (130, 120/140) comprises: a first electrode (fig 4, 120) ; a second electrode (140) ; and an emission layer (130a including EML1) electrically connected to the first electrode (120) through a first contact portion (portion in physical contact) and electrically connected to the second electrode (140) through a second contact portion (portion in physical contact) , wherein the emission layer (130a including EML1) comprises: a first sub-emission layer comprising a first N-type semiconductor layer (ETL is N-type) , a first P-type semiconductor layer (H TL is P-type) , and a first active layer (EML1) between the first N-type semiconductor layer (ETL) and the first P-type semiconductor layer (HTL) ; and a second sub-emission layer (130c) comprising a second N-type semiconductor layer (ETL) , a second P-type semiconductor layer (HTL) , and a second active layer (EML2) between the second N-type semiconductor layer (ETL) and the second P-type semiconductor layer (HTL) , and wherein the first sub-emission layer and the second sub-emission layer are electrically connected in series between the first electrode and the second electrode (fig 4, 130a and 130c are connected in series between 120 and 140) . As to claim 2, Ryu discloses the display device of claim 1 (paragraphs above), wherein the pixel circuit layer comprises a first power source ( anode 121 ) and a second power source ( cathode 1 4 1) , wherein the first power source is electrically connected to the pixel circuit layer (TFT layer) , and wherein the first sub-emission layer (EML1) and the second sub-emission layer (EML2) are electrically connected between the pixel circuit layer (TFT layer) and the second power source (cathode 141) . As to claim 4 , Ryu discloses the display device of claim 1 (paragraphs above), wherein the emission layer (130) further comprises an electrode layer (CGL) between the first P-type semiconductor layer (HTL) and the second N-type semiconductor layer (ETL) . As to claim 5 , Ryu discloses the display device of claim 1 (paragraphs above), wherein the first P-type semiconductor layer and the second N-type semiconductor layer contact each other (fig 4, HTL and ETL contact each other through adjacent layers) . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 6 -8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryu in view of Jo et al. (US Pub. No. 2020/0194503 A1), hereafter referred to as Jo . As to claim 6 , Ryu discloses the display device of claim 1 (paragraphs above), Ryu does not disclose a quantum-dot layer on the emission layer, wherein light emitted by the emission layer passes through the quantum-dot layer. Nonetheless, Jo discloses a display device comprising a quantum-dot layer on an emission layer, wherein light emitted by the emission layer passes through the quantum-dot layer ( fig 1, quantum-dot layer 230R/G/B for the sub-pixels; [0004] ) . It would have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to include the quantum-dot layer Jo in the display of Ryu since this will improve the emission spectrum of the light emitted from each pixel of the display. As to claim 7 , Ryu in view of Jo disclose the display device according to claim 6 (paragraphs above). Ryu further discloses a first sub-pixel area from which light of a first color is emitted (P1; [0047]) ; a second sub-pixel area from which light of a second color is emitted (P2; [0047]) ; and a third sub-pixel area from which light of a third color is emitted (P3, [0047]) , wherein the emission layer comprises a first emission layer overlapping the first sub-pixel area (131 overlapping P1) , a second emission layer overlapping the second sub-pixel area (132 overlapping P2) , and a third emission layer overlapping the third sub-pixel area in a plan view (133 overlapping P3) . As to claim 8 , Ryu in view of Jo disclose the display device according to claim 7 (paragraphs above). Ryu further discloses wherein the first sub-emission layer and the second sub-emission layer form a light emitting unit (fig 4, EML1 and EML2) , wherein the light emitting unit comprises a first light emitting unit (130a) and a second light emitting unit ( 130b ) , and wherein the first light emitting unit and the second light emitting unit are in each of the first sub-pixel area, the second sub-pixel area, and the third sub-pixel area (130a and 130b in each of P1, P2, and P3) . As to claim 1 2, Ryu discloses a display device (100) comprising sub-pixels (P1-P3), the display device comprising: a pixel circuit layer (111 with TFT) comprising a base layer (111) and a pixel circuit (TFT) on the base layer (111) ; and a light emitting element (130) on the pixel circuit layer (111) , wherein the light emitting element (130) comprises: a first electrode (120) ; a second electrode (140) ; an emission layer (EML1) electrically connected to the first electrode 120) through a first contact portion (portion contacting EML1) and electrically connected to the second electrode (140) through a second contact portion (portion contacting EML1) , and wherein the second contact portion comprises contact portions in the sub-pixel area of each of the sub-pixels (portions of contact in each sub-pixel). Ryu does not disclose a quantum- dot layer on the emission layer, wherein each of the sub-pixels has a sub-pixel area overlapping the quantum-dot layer in a plan view . Nonetheless, Jo discloses a display device comprising a quantum-dot layer on an emission layer, wherein each of the sub-pixels has a sub-pixel area overlapping the quantum-dot layer in a plan view (fig 1, quantum-dot layer 230R/G/B for the sub-pixels; [0004]) . It would have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to include the quantum-dot layer Jo in the display of Ryu since this will improve the emission spectrum of the light emitted from each pixel of the display. Allowable Subject Matter Claims 13- 20 are allowed. Claims 3 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the emission layer further comprises a distributed Bragg reflective layer on the second P-type semiconductor layer, wherein the first sub-emission layer further comprises a first superlattice layer between the first N-type semiconductor layer and the first active layer and a first electron blocking layer between the first active layer and the first P-type semiconductor layer, and wherein the second sub-emission layer further comprises a second superlattice layer between the second N-type semiconductor layer and the second active layer and a second electron blocking layer between the second active layer and the second P-type semiconductor layer , as recited in claim 3; or manufacturing a second sub-emission layer comprising a second N-type semiconductor layer, a second P-type semiconductor layer, and a second active layer between the second N-type semiconductor layer and the second P-type semiconductor layer; and forming a first electrode electrically connected to the first N-type semiconductor layer at a first contact portion and a second electrode electrically connected to the second P-type semiconductor layer at a second contact portion, and wherein the first sub-emission layer and the second sub-emission layer are electrically connected in series between the first electrode and the second electrode , as recited in claim 13; or wherein the manufacturing of the emission layer comprises disposing an undoped semiconductor layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on a growth substrate, wherein the emission layer forms a first light emitting unit and a second light emitting unit, and wherein the forming of the second electrode comprises forming a (2-1) th electrode corresponding to the first light emitting unit and a (2-2) th electrode corresponding to the second light emitting unit , as recited in claim 20 ; or wherein the second electrode comprises a (2-1) th electrode corresponding to the first light emitting unit and a (2-2) th electrode corresponding to the second light emitting unit , as recited in claim 9 . Dependent claims 10-11 and 14-19 are allowable because of their dependence from one of claim s 9 or 13. Pertinent Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2020/0185469; US Pub. No 2019/0355786 and US Pub. No 2022/0246802A1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT SHAUN M CAMPBELL whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3830 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT MWFS: 7:30-6pm Thurs 1-2pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration t ool. To schedule an interview, a pplicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAUN M CAMPBELL/ Primary Examiner, Art Unit 2893 3/2 /2026