DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) submitted on December 26, 2023 and September 27, 2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 5 and 11 are objected to because of the following informalities: “and manganese” should read “and/or manganese” (claim 5, line 3 and claim 11, line 3). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,537,913 B2 (hereinafter “Modak”).
Regarding claim 1, Modak discloses a method of forming patterns, comprising:
providing a first dielectric layer (101; Fig. 1a; col. 1, line 64) having a first opening (103, 104; Fig. 1a; col. 1, lines 66-67);
depositing a first seed layer (106; Fig. 1b; col. 3, lines 1-11; note: Applicant’s specification states in [0015] that tantalum, tantalum nitride and titanium nitride may each serve as a material of a seed layer) and a first conductive layer (105; Fig. 1b; col. 3, lines 12-21) in the first opening;
removing a portion of the first conductive layer to form a recess (Fig. 1c; col. 4, lines 14-18); and
depositing a vacancy migration blocking layer (107; Fig. 1d; col. 4, lines 19-29; note: Applicant’s specification states in [0024] that tantalum, tantalum nitride, titanium and titanium nitride may each serve as a material of a vacancy migration blocking layer) and a second conductive layer (108; Fig. 1d; col 4, lines 30-32) in the recess such that the first seed layer, the first conductive layer, the vacancy migration blocking layer, and the second conductive layer form a first pattern (106, 111, 107, 109; Fig. 1e; col. 4, lines 40-50).
Regarding claim 6, Modak discloses the vacancy migration blocking layer is formed to sandwich between the first conductive layer and the second conductive layer (Fig. 1e).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Modak in view of US 6,136,682 (hereinafter “Hegde”).
Regarding claim 2, Modak discloses the method of claim 1.
Modak does not disclose depositing a second dielectric layer and a third dielectric layer on the first dielectric layer and the first pattern; removing a portion of the third dielectric layer to form a second opening in the third dielectric layer; removing a portion of the second dielectric layer to form a third opening in the second dielectric layer; and depositing a second seed layer and a third conductive layer into the second opening and the third opening to form a second pattern.
Hegde teaches depositing a second dielectric layer (114; Fig. 8; col. 6, line 10) and a third dielectric layer (118; Fig. 8; col. 6, line 13) on the first dielectric layer (102; Fig. 8; col. 5, line 34) and the first pattern (106, 108, 110a; Fig. 8; col. 6, lines 1-5);
removing a portion of the third dielectric layer to form a second opening in the third dielectric layer (Fig. 8; col. 6, lines 16-21);
removing a portion of the second dielectric layer to form a third opening in the second dielectric layer (Fig. 8; col. 6, lines 16-21); and
depositing a second seed layer (120, 122; Fig. 9; col. 6, lines 22-24) and a third conductive layer (124; Fig. 9; col. 6, lines 24-26) into the second opening and the third opening to form a second pattern (120, 122, 124a; Fig. 10; col. 6, lines 27-31).
Modak and Hegde are analogous art because they both are directed to semiconductor manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Modak with the specified features of Hegde because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to deposit a second dielectric layer and a third dielectric layer on the first dielectric layer and the first pattern, to remove a portion of the third dielectric layer to form a second opening in the third dielectric layer, to remove a portion of the second dielectric layer to form a third opening in the second dielectric layer, and to deposit a second seed layer and a third conductive layer into the second opening and the third opening to form a second pattern, as taught by Hegde, in order to form a dual damascene interconnect structure.
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0096098 A1 (hereinafter “Yang”) in view of US 2022/0415817 A1 (hereinafter “Lin”).
Regarding claim 7, Yang discloses in Fig. 2 and related text a package ([0023]), comprising:
a first die (205; [0024]);
a first encapsulant (209; [0026]) laterally encapsulating the first die; and
a redistribution structure (207; [0024]) disposed on the first die and the first encapsulant.
Yang does not disclose the redistribution structure comprising: a first dielectric layer; and a first conductive pattern embedded in the first dielectric layer, wherein the first conductive pattern comprises a seed layer, a first conductive layer, a vacancy migration blocking layer, and a second conductive layer, and the vacancy migration blocking layer is sandwiched between the first conductive layer and the second conductive layer.
Lin teaches in Figs. 11, 12 and related text the redistribution structure (300A; [0062]) comprising:
a first dielectric layer (104b; [0063]); and
a first conductive pattern embedded in the first dielectric layer, wherein the first conductive pattern comprises a seed layer (116b; [0047] and [0063]), a first conductive layer (112b; [0044] and [0063]), a vacancy migration blocking layer (114b; [0045] and [0063]; note: Applicant’s specification states in [0024] that tantalum (Ta), titanium (Ti) and cobalt (Co) may each serve as a material of a vacancy migration blocking layer), and a second conductive layer (118b; [0048] and [0063]), and the vacancy migration blocking layer is sandwiched between the first conductive layer and the second conductive layer.
Yang and Lin are analogous art because they both are directed to semiconductor manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang with the specified features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the redistribution structure to comprise: a first dielectric layer; and a first conductive pattern embedded in the first dielectric layer, wherein the first conductive pattern comprises a seed layer, a first conductive layer, a vacancy migration blocking layer, and a second conductive layer, and the vacancy migration blocking layer is sandwiched between the first conductive layer and the second conductive layer, as taught by Lin, in order to improve the electromigration resistance of the redistribution structure.
Regarding claim 9, Yang in view of Lin disclose the package of claim 7.
Yang does not disclose the vacancy migration blocking layer exhibits a U-shape in a cross-sectional view.
Lin teaches in Fig. 11 and related text the vacancy migration blocking layer (114b) exhibits a U-shape in a cross-sectional view.
Yang and Lin are analogous art because they both are directed to semiconductor manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang in view of Lin with the specified features of Lin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the vacancy migration blocking layer to exhibit a U-shape in a cross-sectional view, as taught by Lin, in order for the vacancy migration blocking layer to surround the via portion of the second conductive layer.
Moreover, it has been held that change in shape, in the absence of persuasive evidence that the particular configuration is significant, is a matter of design choice involving only ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04(IV)(B).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lin as applied to claim 7 above, and further in view of US 2017/0125376 A1 (hereinafter “Yeh”).
Regarding claim 15, Yang in view of Lin disclose the package of claim 7.
Yang in view of Lin do not disclose a second die disposed on the first die opposite to the redistribution structure; a dummy die adjacent to the second die; and a second encapsulant laterally encapsulating the second die and the dummy die.
Yeh teaches in Fig. 11A and related text a second die (102B; [0042]) disposed on the first die (102A; [0042]) opposite to the redistribution structure (126; [0038]);
a dummy die (202; [0042]) adjacent to the second die; and
a second encapsulant (120; [0035]) laterally encapsulating the second die and the dummy die.
Yang, Lin and Yeh are analogous art because they each are directed to semiconductor manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang in view of Lin with the specified features of Yeh because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a second die disposed on the first die opposite to the redistribution structure, to provide a dummy die adjacent to the second die, and to form a second encapsulant laterally encapsulating the second die and the dummy die, as taught by Yeh, in order to provide a system-in-package (SiP) solution (Yeh: [0021]), and in order to reduce coefficient of thermal expansion (CTE) mismatch amongst various features in the package (Yeh: [0042]).
Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Modak.
Regarding claim 16, Yang discloses in Fig. 2 and related text a manufacturing method of a package ([0023]), comprising:
providing a die (205; [0024]);
encapsulating the die by an encapsulant (209; [0026]); and
forming a redistribution structure (207; [0024]) on the die and the encapsulant.
Yang does not disclose the forming the redistribution structure on the die and the encapsulant comprising: forming a first dielectric layer on the die, wherein the first dielectric layer has a first opening; filling the first opening by a first seed layer and a first conductive layer; removing a portion of the first conductive layer to form a recess; and filling the recess by a vacancy migration blocking layer and a second conductive layer such that the first seed layer, the first conductive layer, the vacancy migration blocking layer, and the second conductive layer form a first conductive pattern.
Modak teaches in Figs. 1a-1e and related text forming a first dielectric layer (101; Fig. 1a; col. 1, lines 64-65) on the die (100; Fig. 1a; col. 1, lines 13-15 and col. 2, lines 1-14), wherein the first dielectric layer has a first opening (103, 104; Fig. 1a; col. 1, lines 66-67);
filling the first opening by a first seed layer (106; Fig. 1b; col. 3, lines 1-11; note: Applicant’s specification states in [0015] that tantalum, tantalum nitride and titanium nitride may each serve as a material of a seed layer) and a first conductive layer (105; Fig. 1b; col. 3, lines 12-21);
removing a portion of the first conductive layer to form a recess (Fig. 1c; col. 4, lines 14-18); and
filling the recess by a vacancy migration blocking layer (107; Fig. 1d; col. 4, lines 19-29; note: Applicant’s specification states in [0024] that tantalum, tantalum nitride, titanium and titanium nitride may each serve as a material of a vacancy migration blocking layer) and a second conductive layer (108; Fig. 1d; col. 4, lines 30-32) such that the first seed layer, the first conductive layer, the vacancy migration blocking layer, and the second conductive layer form a first conductive pattern (106, 111, 107, 109; Fig. 1e; col. 4, lines 40-50).
Yang and Modak are analogous art because they both are directed to semiconductor manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang with the specified features of Modak because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a first dielectric layer on the die, wherein the first dielectric layer has a first opening; to fill the first opening by a first seed layer and a first conductive layer; to remove a portion of the first conductive layer to form a recess; and to fill the recess by a vacancy migration blocking layer and a second conductive layer such that the first seed layer, the first conductive layer, the vacancy migration blocking layer, and the second conductive layer form a first conductive pattern, as taught by Modak, in order to enable an aluminum capping layer to be formed on top of a copper interconnect pad in a self-aligned manner, and without having to apply a lithography, etch, photoresist ash, and post etch clean sequence, which adds complexity and expense (Modak: col. 4, lines 66-67 and col. 5, lines 1-3).
Regarding claim 20, Yang in view of Modak disclose the method of claim 16.
Yang does not disclose the vacancy migration blocking layer is formed to sandwich between the first conductive layer and the second conductive layer.
Modak teaches in Fig. 1e and related text the vacancy migration blocking layer (107) is formed to sandwich between the first conductive layer (111) and the second conductive layer (109).
Yang and Modak are analogous art because they both are directed to semiconductor manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang in view of Modak with the specified features of Modak because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the vacancy migration blocking layer to sandwich between the first conductive layer and the second conductive layer, as taught by Modak, in order to prevent intermixing of the copper atoms in the first conductive layer and the aluminum atoms in the second conductive layer.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Modak as applied to claim 16 above, and further in view of Hegde.
Regarding claim 17, Yang in view of Modak disclose the method of claim 16.
Yang in view of Modak do not disclose the step of forming the redistribution structure further comprises: forming a second dielectric layer and a third dielectric layer on the first dielectric layer and the first conductive pattern; removing a portion of the third dielectric layer to form a second opening in the third dielectric layer; removing a portion of the second dielectric layer to form a third opening in the second dielectric layer; and filling the second opening and the third opening by a second seed layer and a third conductive layer to form a second conductive pattern.
Hegde teaches forming a second dielectric layer (114; Fig. 8; col. 6, line 10) and a third dielectric layer (118; Fig. 8; col. 6, line 13) on the first dielectric layer (102; Fig. 8; col. 5, line 34) and the first conductive pattern (106, 108, 110a; Fig. 8; col. 6, lines 1-5);
removing a portion of the third dielectric layer to form a second opening in the third dielectric layer (Fig. 8; col. 6, lines 16-21);
removing a portion of the second dielectric layer to form a third opening in the second dielectric layer (Fig. 8; col. 6, lines 16-21); and
filling the second opening and the third opening by a second seed layer (120, 122; Fig. 9; col. 6, lines 22-24) and a third conductive layer (124; Fig. 9; col. 6, lines 24-26) to form a second conductive pattern (120, 122, 124a; Fig. 10; col. 6, lines 27-31).
Yang, Modak and Hegde are analogous art because they each are directed to semiconductor manufacturing and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang in view of Modak with the specified features of Hegde because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a second dielectric layer and a third dielectric layer on the first dielectric layer and the first conductive pattern; to remove a portion of the third dielectric layer to form a second opening in the third dielectric layer; to remove a portion of the second dielectric layer to form a third opening in the second dielectric layer; and to fill the second opening and the third opening by a second seed layer and a third conductive layer to form a second conductive pattern, as taught by Hegde, in order to form a dual damascene interconnect structure.
Allowable Subject Matter
Claims 3-5, 8, 10-14, 18 and 19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to anticipate or render obvious “the step of removing the portion of the first conductive layer and the step of removing the portion of the second dielectric layer use a same photomask” as recited in claims 3 and 18, “the second pattern is formed to land on a span of the second conductive layer” as recited in claim 4, “a material of the first conductive layer and a material of the second conductive layer comprise copper” as recited in claim 5, “the first conductive layer is sandwiched between the seed layer and the vacancy migration blocking layer” as recited in claim 8, “a material of the first conductive layer and a material of the second conductive layer are the same” as recited in claim 10, “the via portion is embedded in the second dielectric layer and is in physical contact with the first conductive pattern” as recited in claim 12, and “the second conductive pattern is formed to land on a span of the second conductive layer” as recited in claim 19. Claim 11 depends from claim 10 and therefore would be allowable at least by virtue of its dependency. Claims 13 and 14 depend from claim 12 and therefore would be allowable at least by virtue of their dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811