Prosecution Insights
Last updated: April 19, 2026
Application No. 18/396,713

SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE

Non-Final OA §102§112
Filed
Dec 27, 2023
Examiner
OWENS, DOUGLAS W
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
84%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
265 granted / 328 resolved
+12.8% vs TC avg
Minimal +3% lift
Without
With
+2.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
29 currently pending
Career history
357
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
35.9%
-4.1% vs TC avg
§102
36.8%
-3.2% vs TC avg
§112
18.0%
-22.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 328 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 – 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “modifying the thick-metal density range.” The scope of the scope of the claim is unclear since it is not known what “modifying” involves. Is the modifying step part of an abstract idea that would be a part of the design process? Does the structure have an initial density range that is modified in some direction to constrain warpage? How is the density range modified? Is the density range increased or decreased? What is the process applied to modify the range? Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, 5, 8, and 9 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US Patent Application Publication No. 2017/0372997 to Tsukamoto. Regarding claim 1, as best understood, Tsukamoto teaches a method of fabricating a semiconductor structure fabricating the semiconductor structure by forming the layers of metal patterns (30, 104) on the wafer substrate, and a thickness of the thick-metal layer (30) is twice or more of a thickness of one of the layers of metal patterns next to the thick-metal layer (¶ [0091]). The abstract limitations of providing a density range for a model structure and modifying the thick-metal density range have not been given patentable weight. As best understood, these limitation are not positive recitations of any processing steps, but are drawn to the design process, which are considered mere mental steps that could also be done with pencil and paper. Claims 2, 5, 8, and 9 have not been given patentable weight, since the claims seem to be drawn to the abstract idea of the design process, not involving any fabrication steps. Allowable Subject Matter Claims 10 – 20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or reasonably suggest a semiconductor structure as recited in claim 10 including “first dummy patterns, a first overall distribution density of the first electric transmission patterns and the first dummy patterns is greater than the first pattern distribution density by ≤125% of the first pattern distribution density”; nor a semiconductor structure as recited in claim 18 including “dummy patterns, wherein an overall distribution density of the electric transmission patterns and the dummy patterns is greater than the pattern distribution density by ≤20% of the pattern distribution density.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2016/0300845 to Ishizaki et al. teach a semiconductor structure and method of fabrication including multiple metal layers and relaxed warpage. Ishizaki et al. do not teach the thick metal layer or first dummy patterns. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DOUGLAS W. OWENS, Esq. Primary Patent Examiner Art Unit 2897 /DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Dec 27, 2023
Application Filed
Feb 24, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12593716
SUBSTRATE ASSEMBLY AND ELECTRONIC DEVICE INCLUDING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12588538
SEMICONDUCTOR DEVICE HAVING WIRED UNDER BUMP STRUCTURE AND METHOD THEREFOR
2y 5m to grant Granted Mar 24, 2026
Patent 12581937
INTEGRATED DEVICE COMPRISING METALLIZATION INTERCONNECTS
2y 5m to grant Granted Mar 17, 2026
Patent 12564085
MICROELECTRONIC ASSEMBLY WITH UNDERFILL FLOW CONTROL
2y 5m to grant Granted Feb 24, 2026
Patent 12563882
ELECTRONIC DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
84%
With Interview (+2.8%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 328 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month