DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Embodiment 1 of Figure 1, Claims 1-12, in the reply filed on 04/17/2026 is acknowledged.
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/17/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6, which is depend on claim 5, and then claim 2, recites the plurality of supporting sections are disposed beneath the second dielectric, which is in conflict with claim 2, which recites the plurality of supporting section are disposed in the second dielectric. It is unclear how the plurality of supporting sections are disposed in the second dielectric can also being disposed beneath the second dielectric?
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2020/0373305) in view of Wu (US 2022/0059458).
Regarding claim 1, Hsu discloses, as shown in Figure 1, a semiconductor device comprising:
a substrate (110) with a drain region (not shown, [0034]) and a source region (not shown, [0035]) disposed in the substrate;
a gate structure (120) disposed over the substrate and between the drain region and the source region;
a first dielectric (131) disposed over the substrate and covering the substrate and the gate structure;
a plug (140) disposed in the first dielectric, wherein the plug includes a first portion (a portion of 140 in 131) extending through the first dielectric and contacting the source region of the substrate ([0034]), and a second portion (another portion of 140 protruding from 131) protruding from the first dielectric;
a storage node landing pad (150) disposed on an exposed part of the second portion of the plug;
a second dielectric (132) disposed over the first dielectric and covering the storage node landing pad;
a bit line (160) extending through the second dielectric and the first dielectric and connected to the substrate [0035];
a third dielectric (133) disposed over the bit line; and
a storage node (170) disposed over the third dielectric, wherein the storage node extends through the third dielectric and the second dielectric and contacts the storage node landing pad.
Hsu does not disclose at least one air gap disposed in the second dielectric. However, Wu discloses a semiconductor device comprising at least one air gap (136a-136c) disposed in a second dielectric (123’). Note [0046] and Figures 1-2 of Wu. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the second dielectric of Hsu comprising at least one air gap disposed in therein, such as taught Wu in order to further reduce the parasitic capacitance between the bit line and the plug.
Regarding claim 2, Hsu and Wu disclose the semiconductor device further comprising a plurality of supporting sections (123’ between 136a-c, Figure 1) disposed in the second dielectric, wherein the supporting sections are spaced apart from each other to define the air gaps.
Regarding claim 3, Hsu and Wu disclose the supporting sections are separated by the air gaps (Figure 1).
Regarding claim 4, Hsu and Wu disclose the plurality of supporting sections are formed during the forming of the air gaps.
Note that the term “are formed during the forming of the air gaps” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 5, Hsu and Wu disclose the plurality of supporting sections are disposed between an upper metal line (160) and a lower metal line (120).
Regarding claim 7, Hsu and Wu disclose the air gaps extend through the second dielectric (Figure 1).
Regarding claim 8, Hsu and Wu do not disclose a width of the air gap is less than a width of the gate structure in a sectional view. However, the selection of these parameters such as energy, concentration, temperature, time, speed, molar fraction, depth, width, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, width, thickness, etc., or in combination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Alter 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
Regarding claim 9, Hsu and Wu disclose the claimed invention including the semiconductor device as explained in the above rejection. Hsu and Wu do not disclose a centerline of the air gap is aligned with a centerline of the gate structure. However, by adjusting the position of the centerline of the air gap in relative to the centerline of the gate structure, the parasitic capacitance would be reduced as the desired configuration. Therefore, it would have been obvious to one skill in the art at the time the invention was made to adjust the centerline of the air gap of Hsu and Wu being aligned with the centerline of the gate structure in order to have the desired configuration.
Regarding claim 10, Hsu and Wu disclose the semiconductor device further comprising a bit line landing pad (180) on the drain region of the substrate, wherein the bit line connects to the drain region of the substrate by contacting the bit line landing pad ([0035], Figure 1).
Regarding claim 11, Hsu and Wu disclose the plug (140) comprises copper and the storage node landing pad (150) comprises Cu3Ge [0034].
Regarding claim 12, Hsu and Wu disclose the gate structure further comprises a silicide (121), a polycrystalline silicon (122), a gate oxide (123), and a spacer (124) ([0033], Figure 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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