Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yonemoto (US 2021/0185251 A1) in view of Shibata (US 2021/0305360 A1) and Lee et al., hereinafter Lee560 (US 2012/0248560 A1).
Regarding independent claim 1: Yonemoto teaches (e.g., Fig. 3) a semiconductor device, comprising:
a microlens ([0081]: 53);
a color filter ([0081]: 52) disposed adjacent the microlens;
an epitaxial substrate layer ([0081] and [0085]-[0089]: semiconductor substrate 12; photodiode and photoelectric conversion, [0106]: inherently use an epitaxial semiconductor layer) disposed adjacent the color filter opposite the microlens; and
a trench capacitor ([0106]: C1) formed in the epitaxial substrate layer and having sidewall.
Yonemoto does not expressly teach sidewall recesses,
the trench capacitor including a uniform dielectric layer disposed along and within the sidewall recesses.
Shibata teaches (e.g., Figs. 1A-1B and Fig, 2) a semiconductor device comprising a trench capacitor ([0031]-[0032]: TC);
Shibata further teaches that the trench capacitor comprises sidewall recesses ([0031]-[0032] and [0042]: TC).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Yonemoto, the trench capacitor comprises sidewall recesses, as taught by Shibata, for the benefits of increasing the device capacitance, and thus improving the data retention of the integrated circuit device.
Lee560 teaches (e.g., Fig. 1 and 3A-3J) a semiconductor device comprising
a trench (Fig. 1 and Fig. 3B; [0070]) including a uniform dielectric layer ([0036] and [0066]: 120) disposed along and within the sidewall recesses (Fig. 1 and Fig. 3B; [0070]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Yonemoto as modified by Shibata, the device comprising the trench including a uniform dielectric layer disposed along and within the sidewall recesses, as taught by Lee560, for the benefits of better controlling the capacitance of the charge storage device by avoiding discontinuity in the structure.
Regarding claim 2: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the trench capacitor (Yonemoto: Fig. 3, element C1) extends an entire distance of the epitaxial substrate layer (Yonemoto: Fig. 3, element 12).
Regarding claim 5: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the trench capacitor (Yonemoto: C1) extends along two sidewalls of the epitaxial substrate layer (Yonemoto: Fig. 3; element 12).
Regarding claim 6: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the trench capacitor (Yonemoto: C1) is a first trench capacitor (Yonemoto: right side capacitor C1) and is formed along a first sidewall of the epitaxial substrate layer (Yonemoto: right sidewall of substrate 12), and
the semiconductor device further comprises:
a second trench capacitor (Yonemoto: [0071] and [0093]: second capacitor C1 adjacent left side of first trench capacitor C1) formed along a second sidewall of the epitaxial substrate layer (Yonemoto: 12).
Regarding claim 7: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 6, on which this claim depends,
Yonemoto as modified by Shibata teaches that the sidewall recesses of the first trench capacitor (Yonemoto: [0071] and [0093]: first trench capacitor C1) are first sidewall recesses (Shibata: [0031]-[0032] and [0042]: TC), and
the second trench capacitor (Yonemoto: [0071] and [0093]: a second trench capacitor C1 adjacent left side of first trench capacitor C1) includes a second sidewall recesses in the second sidewall (Shibata: [0031]-[0032] and [0042]: TC).
Regarding claim 9: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the trench capacitor is a first trench capacitor (Yonemoto: [0071] and [0093]: first trench capacitor C1) and is formed along a sidewall of the epitaxial substrate layer (Yonemoto: 12), and the semiconductor device further comprises:
a second trench capacitor (Yonemoto: [0071] and [0093]: second trench capacitor C1 adjacent left side of first trench capacitor C1) formed along the sidewall of the epitaxial substrate layer (Yonemoto: 12).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yonemoto (US 2021/0185251 A1) in view of Shibata (US 2021/0305360 A1) and Lee et al., hereinafter Lee560 (US 2012/0248560 A1) as applied above and further in view of Takizawa et al. (US 2019/0019820 A1).
Regarding claim 3: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 1, on which this claim depends,
the trench capacitor (Yonemoto: Fig. 3, element C1) extends from a surface of the epitaxial substrate layer (Yonemoto: Fig. 3, element 12) that is opposite the color filter (Yonemoto: Fig. 3, element 52) and only partially through the epitaxial substrate layer (Yonemoto: Fig. 3, element 12).
Yonemoto does not expressly teach that the trench capacitor extends from a surface of the epitaxial substrate layer only partially through the epitaxial substrate layer.
Takizawa teaches (e.g., Figs.5A-5C) a semiconductor device, comprising a substrate ([0125]: 70) and a trench capacitor ([0110], [0115] and [0123]: 56);
Takizawa further teaches that the trench capacitor ([0110], [0115] and [0123]: 56) extends from a surface of the epitaxial substrate layer ([0125]: 70) and only partially through the epitaxial substrate layer (70).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Yonemoto as modified by Shibata, the
trench capacitor extending from a surface of the epitaxial substrate layer and only partially through the epitaxial substrate layer, as taught by Takizawa, for the benefits of optimizing the isolation structure length and depth to only include the required depth for storing the image data and at the same time reducing manufacturing material needed.
Regarding claim 4: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 1, on which this claim depends,
wherein the trench capacitor (Yonemoto: Fig. 3, element C1) extends from a surface of the epitaxial substrate layer (Yonemoto: Fig. 3, element 12) that is adjacent to the color filter (Yonemoto: Fig. 3, element 52) and through the epitaxial substrate layer (Yonemoto: Fig. 3, element 12).
Yonemoto does not expressly teach that the trench capacitor extends from a surface of the epitaxial substrate layer only partially through the epitaxial substrate layer.
Takizawa teaches (e.g., Figs.5A-5C) a semiconductor device, comprising a substrate ([0125]: 70) and a trench capacitor ([0110], [0115] and [0123]: 56);
Takizawa further teaches that the trench capacitor ([0110], [0115] and [0123]: 56) extends from a surface of the epitaxial substrate layer ([0125]: 70) and only partially through the epitaxial substrate layer (70).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Yonemoto as modified by Shibata, the
trench capacitor extending from a surface of the epitaxial substrate layer and only partially through the epitaxial substrate layer, as taught by Takizawa, for the benefits of optimizing the isolation structure length and depth to only include the required depth for storing the image data and at the same time reducing manufacturing material needed.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yonemoto (US 2021/0185251 A1) in view of Shibata (US 2021/0305360 A1) and Lee et al., hereinafter Lee560 (US 2012/0248560 A1) as applied above and further in view of Park et al. (US 2015/0028450 A1).
Regarding claim 8: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 6, on which this claim depends,
the first trench capacitor is formed to a first depth (Yonemoto: [0071] and [0093]: first trench capacitor C1 formed to a first depth) within the epitaxial substrate layer (Yonemoto: 12).
Yonemoto as modified by Shibata does not expressly teach that
the second trench capacitor is formed to a second depth within the epitaxial substrate layer that is different from the first depth.
Park teaches (e.g., Fig. 3) a device comprising a first trench capacitor ([0097]-[0098]: 70QB) formed to a first depth within a substrate layer (20);
Parker further teaches that a second trench capacitor ([0097]-[0098]: 70QA) is formed to a second depth (Fig. 3; [0097]-[0098]) within the epitaxial substrate layer ([0097]: 20) that is different from the first depth ([0098]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Yonemoto as modified by Shibata, the second trench capacitor being formed to a second depth within the epitaxial substrate layer that is different from the first depth, as taught by Park, for the benefits of increasing versatility of data storage based on desired data storage device capacity.
Regarding claim 10: Yonemoto, Shibata and Lee560 teach the claim limitation of the semiconductor device of claim 9, on which this claim depends,
wherein the trench capacitor is formed to a first depth (Yonemoto: [0071] and [0093]: first trench capacitor C1 formed to a first depth) within the epitaxial substrate layer (Yonemoto: 12).
Yonemoto as modified by Shibata does not expressly teach that
the second trench capacitor is formed to a second depth within the epitaxial substrate layer that is different from the first depth.
Park teaches (e.g., Fig. 3) a device comprising a first trench capacitor ([0097]-[0098]: 70QB) formed to a first depth within a substrate layer ([0097]: 20);
Parker further teaches that a second trench capacitor ([0097]-[0098]: 70QA) is formed to a second depth (Fig. 2-3B; [0097]-[0098]) within the epitaxial substrate layer ([0097]: 20) that is different from the first depth ([0098]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Yonemoto as modified by Shibata, the second trench capacitor being formed to a second depth within the epitaxial substrate layer that is different from the first depth, as taught by Park, for the benefits of increasing versatility of data storage based on desired data storage device capacity.
Claims 11-14, 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., hereinafter Lee691, (US 2018/0190691 A1) in view of Shibata (US 2021/0305360 A1) and Lee et al., hereinafter Lee560 (US 2012/0248560 A1).
Regarding independent claim 11: Lee691 teaches (e.g., Figs. 2-4) an optical sensor including an array of pixel circuits ([0033]-[0037]), each pixel circuit comprising:
a microlens ([0041]: ML);
a color filter ([0040]: CF) disposed adjacent the microlens;
an epitaxial substrate layer ([0040]: 100; semiconductor substrate 100; photodiode and photoelectric conversion [0031], inherently comprises an epitaxial semiconductor layer) disposed adjacent the color filter (CF) opposite the microlens (ML); and
an isolation trench ([0025]-[0026]: isolation structure 110 including trench DTI) formed in the epitaxial substrate layer (100) and having sidewalls with sidewall recesses (Fig. 2; [0025]) formed therein,
the sidewall recesses having insulating material ([0030]: IL) disposed thereon and the isolation trench (isolation structure 110 including trench DTI) having a conductive material ([0030]: CL) disposed therein.
Lee691 does not expressly teach
concave sidewall recesses extending into the epitaxial substrate layer,
a uniform layer of insulating material disposed thereon.
Shibata teaches (e.g., Figs. 1A-1B and Fig, 2) a semiconductor device comprising a trench capacitor ([0031]-[0032]: TC) and a substrate ([0031]-[0032]: 10);
Shibata further teaches that the trench capacitor comprises concave sidewall recesses ([0031]-[0032] and [0042]: TC) extending into the substrate ([0031]-[0032]: 10) and the insulating material ([0032]-[0033]: 13) disposed thereon.
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Lee691, the trench capacitor comprises sidewall recesses, as taught by Shibata, for the benefits of increasing the device capacitance, and thus improving the data retention of the integrated circuit device.
Lee560 teaches (e.g., Fig. 1 and 3A-3J) a semiconductor device comprising
an isolation trench (Fig. 1 and Fig. 3B; [0070]) including a uniform layer of insulating material ([0036] and [0066]: 120) disposed along and within the sidewall recesses (Fig. 1 and Fig. 3B; [0070]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Lee691 as modified by Shibata, the device comprising the trench including a uniform dielectric layer, as taught by Lee560, for the benefits of better controlling the capacitance of the charge storage device by avoiding discontinuity in the structure.
Regarding claim 12: Lee691 teaches the claim limitation of the optical sensor of claim 11, on which this claim depends,
wherein the isolation trench (isolation structure 110 including trench DTI) extends only partially through the epitaxial substrate layer (100) in a direction perpendicular to the color filter (CF).
Regarding claim 13: Lee691 teaches the claim limitation of the optical sensor of claim 11, on which this claim depends,
wherein the isolation trench (isolation structure 110 including trench DTI) extends along two sidewalls of the epitaxial substrate layer (100).
Regarding claim 14: Lee691 teaches the claim limitation of the optical sensor of claim 11, on which this claim depends,
wherein the isolation trench is a first isolation trench ([0025]-[0026]: right side isolation structure 110 including trench DTI) and is formed along a first sidewall of the epitaxial substrate layer (100), and
the optical sensor further comprises:
a second isolation trench ([0025]-[0026]: second isolation trench isolation structure 110 including trench DTI on left side and adjacent the first isolation trench) formed along a second sidewall of the epitaxial substrate layer (100).
Regarding claim 16: Lee691 teaches the claim limitation of the optical sensor of claim 11, on which this claim depends,
wherein the isolation trench is a first isolation trench ([0025]-[0026]:right side isolation structure 110 including trench DTI) and is formed along a sidewall of the epitaxial substrate layer (100), and
the optical sensor further comprises:
a second isolation trench ([0025]-[0026]: second isolation trench isolation structure 110 including trench DTI on left side and adjacent the first isolation trench) formed along the sidewall of the epitaxial substrate layer (100).
Regarding independent claim 17: Lee691 teaches (e.g., Figs. 2-4) a method of making a pixel circuit of an optical sensor, comprising:
forming a trench ([0025]-[0026]: T) in an epitaxial substrate layer ([0040]: 100; semiconductor substrate 100; photodiode and photoelectric conversion [0031], inherently comprises an epitaxial semiconductor layer), the trench having sidewall recesses ([0025]-[0026]: sidewall recesses in trench T);
providing an insulating material ([0025]-[0026]: IL) in the sidewall recesses;
providing a conductive material ([0027] and [0034]: CL) in the trench adjacent to the insulating material;
providing a color filter ([0040]: CF) adjacent to a surface (100b) of the epitaxial substrate layer (100); and
forming a microlens ([0041]: ML) adjacent to the color filter.
Lee691 does not expressly teach
forming concave sidewall recesses extending into the epitaxial substrate layer; providing a uniform layer of an insulating material in the sidewall recesses;
Lee691 does not expressly teach
concave sidewall recesses extending into the epitaxial substrate layer,
a uniform layer of insulating material.
Shibata teaches (e.g., Figs. 1A-1B and Fig, 2) a method comprising forming a trench capacitor ([0031]-[0032]: TC) and a substrate ([0031]-[0032]: 10);
Shibata further teaches that the trench capacitor comprises concave sidewall recesses ([0031]-[0032] and [0042]: TC) extending into the substrate layer ([0031]-[0032]: 10).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Lee691, the trench capacitor comprises providing concave sidewall recesses extending into the epitaxial substrate layer, as taught by Shibata, for the benefits of increasing the device capacitance, and thus improving the data retention of the integrated circuit device.
Lee560 teaches (e.g., Fig. 1 and 3A-3J) a method comprising providing an isolation trench (Fig. 1 and Fig. 3B; [0070]) including a uniform layer of insulating material ([0036] and [0066]: 120) disposed along and within the sidewall recesses (Fig. 1 and Fig. 3B; [0070]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Lee691 as modified by Shibata, the device comprising the trench including a uniform dielectric layer, as taught by Lee560, for the benefits of better controlling the capacitance of the charge storage device by avoiding discontinuity in the structure.
Regarding claim 18: Lee691 teaches the claim limitation of the method of claim 17, on which this claim depends,
Lee691 does not expressly teach that the method further comprises forming the trench using a Bosch etching process.
Shibata teaches (e.g., Figs. 1A-1B and Fig, 2) a method comprising forming a trench capacitor ([0031]-[0032]: TC);
Shibata further teaches that the method further teaches forming the trench using a Bosch etching process ([0041], [0045] and [0048]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Lee691, the method of forming the trench using a Bosch etching process, as taught by Shibata, for the benefits of increasing the surface area of the trench and the depth of the trench and thus increasing the capacitance of the device.
Regarding claim 19: Lee691 teaches the claim limitation of the method of claim 17, on which this claim depends, further comprising:
forming the trench ([0028]: T) along a first sidewall of the epitaxial substrate layer ([0028]: 100); and
forming a second trench ([0028]: second trench T left side of first trench T) along a second sidewall of the epitaxial substrate layer (100).
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee691 et al. (US 2018/0190691 A1) in view of Shibata (US 2021/0305360 A1) and Lee et al., hereinafter Lee560 (US 2012/0248560 A1) as applied above and further in view of Park et al. (US 2015/0028450 A1).
Regarding claim 15: Lee691 teaches the claim limitation of the optical sensor of claim 14, on which this claim depends,
wherein the first isolation trench (110) is formed to a first depth within the epitaxial substrate layer (100).
Lee691 does not expressly teach that the second isolation trench is formed to a second depth within the epitaxial substrate layer that is different from the first depth.
Parker further teaches that a second trench capacitor ([0097]-[0098]: 70QA) is formed to a second depth (Fig. 3; [0097]-[0098]) within a substrate layer ([0097]: 20) that is different from the first depth ([0098]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Lee691, the second trench capacitor being formed to a second depth within the substrate layer that is different from the first depth, as taught by Park, for the benefits of increasing versatility of data storage based on desired data storage device capacity.
Regarding claim 20: Lee691 teaches the claim limitation of the method of claim 19, on which this claim depends, further comprising:
forming the trench ([0028]: T) to a first depth (Fig. 2) within the epitaxial substrate layer (100);
Lee691 does not expressly teach forming the second trench to a second depth within the epitaxial substrate layer that is different from the first depth.
Park teaches (e.g., Figs. 2-3) a method comprising forming a first trench capacitor ([0097]-[0098]: 70QB) to a first depth within a substrate layer ([0097]: 20);
Parker further teaches forming a second trench capacitor ([0097]-[0098]: 70QA) to a second depth (Fig. 3; [0097]-[0098]) within a substrate layer ([0097]: 20) that is different from the first depth ([0098]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Lee691, the second trench capacitor being formed to a second depth within the epitaxial substrate layer that is different from the first depth, as taught by Park, for the benefits of increasing versatility of data storage based on desired data storage device capacity.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference or portion of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or the newly added limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812
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