DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Pursuant to the election without traverse on May 15, 2026 of species (a), claims 19-22 are withdrawn from consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner proposes DISPLAY WITH A PIXEL ELECTRODE IN A RECESS
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, US 2018/0108685 A1.
Claim 1: Kim discloses a display device comprising a first pixel (right) and a second pixel (left),
wherein the first pixel and the second pixel each comprises:
a first transistor (154);
a portion of a via layer (81) disposed on the first transistor;
and a portion of a first metal layer (containing 191) disposed on the via layer,
the first pixel further comprises a first pixel electrode (191, right) disposed in the first metal layer,
the second pixel further comprises a second pixel electrode (191, left) disposed in the first metal layer,
and the first pixel electrode has a first end (in T) that faces the second pixel electrode and is positioned at a height lower than the second pixel electrode.
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Note that Kim discloses that “a unit area UA, for example including one pixel PX and one transmitting window TW, may be disposed in a matrix form.” [0045]. Thus it is clearly suggested that the unit is repeated, and thus there will be a unit area to the left of the one shown in FIG. 2. Thus the figure above is a duplication of FIG. 3 to repeat the unit area.
Claim 2 the via layer comprises a crest (180) and a valley (T), a thickness of the crest is greater than a thickness of the valley, the first end is positioned on the valley, and the second pixel electrode is positioned on the crest (FIG. 3).
Claim 3: Kim does not disclose that the thickness of the crest is 3 to 5 times the thickness of the valley. Changes in dimension are not typically a source of patentable distinction absent unexpected results. MPEP 2144.04(IV). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimension or any unexpected results arising therefrom. Where patentability is said to be based upon a variable recited in a claim, the Applicant must show that the variable is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 4: the via layer comprises a valley area, which is an area where the valley is positioned, and the valley area is disposed between the first transistor of the first pixel and the second pixel electrode in plan view (see FIG. above).
Claim 5: Kim discloses a pixel defining layer (360) disposed on the first metal layer, wherein the pixel defining layer comprises a plurality of open portions overlapping at least a part of the first pixel electrode and the second pixel electrode, and the open portions do not overlap the valley area (FIG. 3).
Claim 6: the open portions are disposed on the crest (FIG. 3).
Claim 7: the valley area is disposed to surround at least a portion of the first transistor of the first pixel in plan view (left side, FIG. 2).
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Claim 8: the valley area is disposed to surround a side of the first transistor of the first pixel in plan view, the side facing the second pixel electrode. See FIG. 2 and combined FIG. 3 above.
Claim 9: Kim discloses a third pixel, wherein the third pixel further comprises a third pixel electrode disposed in the first metal layer, and a second end, which is an end of the second pixel electrode, facing the third pixel electrode, is positioned at a height lower than the third pixel electrode. If the unit area is repeated again, then the next pixel would be the third pixel, and the combined FIG. 3 above would be the same, with the second pixel being on the right and the third pixel being on the left.
Claim 16: each of the first pixel and the second pixel further comprises a first capacitor (C) connected to the first transistor, and the first capacitor of each of the first pixel and the second pixel overlaps the crest (see combined FIG. 3).
Claim 17: in a thickness direction of the via layer, no other metal layer is disposed between the first metal layer and the first transistor of the first pixel (FIG. 3).
Claim 18: of the first pixel and the second pixel further comprising: a light emitting layer (370) disposed on the first metal layer; and a second metal layer (270, [0070]) disposed on the light emitting layer, wherein the first transistor is a driving transistor configured to drive light emission of the light emitting layer ([0062]).
Allowable Subject Matter
Claims 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Kim does not disclose a first region overlapping the first end; a second region overlapping the second end; and a third region connecting the first region to the second region, and the examiner did not find a reason it would have been obvious.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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