DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. TW112146351, filed on 11/29/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/28/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 12-15, and 18-20 are rejected under U.S.C. 103 as being unpatentable over Chou et al.; US 2021/0320109 A1; 04/2020 in view of Chen et al.; US 10,541,244 B1; 09/2018 and further in view of Tsuchiaki; US 2007/0246781 A1; 02/2007
Claim 1: Chou discloses a layout pattern of a static random-access memory (SRAM), comprising: a substrate ( [0016] As shown in FIG. 1, a substrate 1 is provided, a plurality of SRAM cells 10 are defined on the substrate 1 ) ; a plurality of diffusion regions ( Fig. 3 diffusion regions 54 ) located on the substrate ( Fig. 1 #1 ) , and the plurality of diffusion region ( Fig. 3 #54 ) at least comprises a first diffusion region ( Fig. 3 first diffusion region 54C ) , a second diffusion region ( Fig. 3 second diffusion region 54B ), a third diffusion region ( Fig. 3 third diffusion region 54A ) and a fourth diffusion region ( Fig. 3 fourth diffusion region 54D ); a plurality of gate structures ( Fig. 3 gate structures 56 ) located on the substrate ( Fig.1 # 1 ), and each gate structure ( Fig. 3 #56 ) extends along a first direction (X direction) ( as shown in Fig. 3 ) and crosses the diffusion regions ( Fig. 3 #54 ) to form a plurality of transistors ( Fig. 3 first pull-up device PU1, second pull-up device PU2, first pull-down PD1, second pull-down PD2, first access transistor PG1, second access transistor PG2 ), wherein the plurality of transistors comprise a first pull-up transistor (PU1) ( Fig. 2: PU1 ), a first pull-down transistor (PD1) ( Fig. 2: PD1 ), a second pull-up transistor (PU2) ( Fig. 2: PU2 ), a second pull-down transistor (PD2) ( Fig. 2: PD2 ), a first access transistor (PG1) ( Fig. 2: PG1 ) and a second access transistor (PG2) ( Fig. 2: PG2 ),
Chou does not appear to disclose the plurality of gate structures comprise a first gate structure, which has a stepped shape when viewed from a top view, and the first gate structure spans the first diffusion region and the second diffusion region to form the first access transistor (PG1), wherein the first diffusion region is adjacent to and in direct contact with the second diffusion region.
Chen ( ‘244 ) discloses the plurality of gate structures ( Fig. 3 #56 ) comprise a first gate structure ( Fig. 3 #56A ), which has a stepped shape when viewed from a top view ( as shown in Fig. 3 ), and the first gate structure ( Fig. 3 #56A ) spans the first diffusion region ( Fig. 3 #54A ) and the second diffusion region ( Fig. 3 #54B ) to form the first access transistor (PG1) ( Fig. 3: PG1A ),
Chen (‘244 ) does not appear to disclose the first diffusion region is adjacent to and in direct contact with the second diffusion region.
However, Tsuchiaki teaches the first diffusion region ( Fig. 11 source/drain diffusion region 106a ) is adjacent to and in direct contact with the second diffusion region ( Fig. 11 source/drain extension region 104a ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Tsuchiaki with Chou and Chen (‘244 ) to implement the plurality of gate structures comprise a first gate structure, which has a stepped shape when viewed from a top view, and the first gate structure spans the first diffusion region and the second diffusion region to form the first access transistor (PG1), wherein the first diffusion region is adjacent to and in direct contact with the second diffusion region because this approach increases device density through layout optimization and improves electrical characteristics of the access transistor PG1.
Claim 2: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 1 ( as discussed above).
Neither Chou nor Tsuchiaki appear to disclose the first gate structure further comprises a first part and a second part, the first part has an L-shape and the second part has a strip shape when viewed from the top view.
However, Chen ( ‘244 ) teaches the first gate structure ( Fig. 3 #56A ) further comprises a first part ( Fig. 3: 56A- 1 and 56A-3 ) and a second part ( Fig. 3 #56A-2 ) , the first part has an L-shape ( as shown in Fig. 3 ) and the second part has a strip shape when viewed from the top view ( as shown in Fig. 3 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Tsuchiaki with Chou and Chen (‘244 ) to implement the first gate structure further comprises a first part and a second part, the first part has an L-shape and the second part has a strip shape when viewed from the top view because this approach would optimize device performance, enhance reliability, and improve manufacturing scalability.
Claim 3: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of SRAM according to claim 2 ( as discussed above).
Neither Chou nor Tsuchiaki appear to disclose the first part has a first edge, a second edge and a third edge extending along the first direction, and the second part has a fourth edge and a fifth edge extending along the first direction.
However, Chen ( ‘244 ) teaches the first part ( Fig. 3: 56A-1 and 56A-3) has a first edge ( Fig. 3: top of 56A-1), a second edge ( Fig. 3: bottom of 56A-1 ) and a third edge ( Fig. 3: top edge of 56A-3 ) extending along the first direction ( as shown in Fig. 3 ), and the second part ( Fig. 3: 56A-2 ) has a fourth edge ( Fig. 3: top of 56-A2 ) and a fifth edge ( Fig.3: bottom of 56A-2 ) extending along the first direction ( as shown in Fig. 3 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Tsuchiaki with Chou and Chen (‘244 ) to implement the first part has a first edge, a second edge and a third edge extending along the first direction, and the second part has a fourth edge and a fifth edge extending along the first direction because this approach allows the gate to control the channel from multiple sides while minimizing leakage and maximizing drive current.
Claim 12: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 2 ( as discussed above ).
Chou teaches a word line ( Fig. 2: WL ) contact electrically connected to the first gate structure ( Fig. 2: PG1 ), wherein the word line ( Fig. 2: WL ) contact does not overlap the second diffusion region ( Fig. 3 #54B ) from the top view ( as shown in Fig. 3).
Claim 13: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 12 ( as discussed above).
Chou teaches a first body contact ( Fig. 3 #62B ) located on and electrically connected to the second diffusion region ( Fig. 3 #54B ).
Claim 14: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 13 ( as discussed above).
Chou teaches a second body contact ( Fig. 3: contact plug 62A ) located on and electrically connected to the third diffusion region ( Fig. 3 #54A ).
Claim 15: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of SRAM according to claim 14 ( as discussed above ).
Chou teaches the distance between the word line contact (Fig. 3 WL ) and the first body contact ( Fig. 3 #62 ) in a second direction (Y direction) is equal to the distance between the word line contact and the second body contact in the second direction ( as shown in Fig. 3 ), wherein the second direction is perpendicular to the first direction ( Fig. 3: X and Y directions are shown to be perpendicular ).
Claim 18: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 1 ( as discussed above).
Chou teaches a bit line contact ( Fig. 2: BL1 ) electrically connecting the first diffusion region ( Fig. 3 #54C connected to BL1 ) and a source of the first access transistor (PG1) ( Fig. 2: PG1 source connection ), and a Vss voltage source ( Fig. 2: Vss ) contact electrically connecting ( Fig. 3: VSS connected to #54C ) the first diffusion region ( Fig. 3 #54C ) and a source of the first pull-down transistor (PD1) ( Fig. 2: PD1 ).
Claim 19: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 18 ( as discussed above).
Chou teaches a node contact ( Fig. 3 contact plug 62 in the middle of #54C ) electrically connected to the first diffusion region ( Fig. 3 #54C ) and located between the first gate structure ( Fig. 3: PG1 is above the node contact in the Y direction ) and a second gate structure ( Fig. 3: PG2 is below the node contact in the Y direction ).
Claim 20: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 19 ( as discussed above).
Chou teaches the bit line contact ( Fig. 3: BL1 ), the Vss voltage source contact ( Fig. 3: Vss contact on right side of figure ) and the node contact ( Fig. 3: contact plug 62 in the middle of the #54C region ) are aligned with each other in a second direction (Y direction) ( as shown in Fig. 3 ).
Claim 6 is rejected under U.S.C. 103 as being unpatentable over Chou et al.; US 2021/0320109 A1; 04/2020 in view of Chen et al.; US 10,541,244 B1; 09/2018 and further in view of Tsuchiaki; US 2007/0246781 A1; 02/2007 as it relates to claim 3 above and further in view of Donnelly et al.; US 2024/0105721 A1; 09/2022
Claim 6: Chou, Chen ( ‘244 ), and Tsuchaiki disclose the layout pattern of SRAM according to claim 3 ( as discussed above).
Neither Chou nor Tsuchaiki appear to disclose the width of the second diffusion region in a second direction (Y direction) is smaller than the distance from the first edge to the third edge in the second direction, wherein the second direction is perpendicular to the first direction.
However, Donnelly teaches the width of the second diffusion region ( Fig. 7A: left side of figure active region 210 ) in a second direction (Y direction) ( as shown in Fig. 7A ) is smaller than the distance from the first edge ( Fig. 7A: top of 356 ) to the third edge ( Fig. 7A: bottom of 356 ) in the second direction, wherein the second direction is perpendicular to the first direction ( as shown in Fig. 7A ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Donnelly with Chou, Chen (‘244 ), and Tsuchiaki to implement the width of the second diffusion region in a second direction (Y direction) is smaller than the distance from the first edge to the third edge in the second direction, wherein the second direction is perpendicular to the first direction because this enables high-density vertical stacking, improved isolation, and accounts for lithography limitations.
Claims 8-11 are rejected under U.S.C. 103 as being unpatentable over Chou et al.; US 2021/0320109 A1; 04/2020 in view of Chen et al.; US 10,541,244 B1; 09/2018 and further in view of Tsuchiaki; US 2007/0246781 A1; 02/2007 as it relates to claim 1 above and further in view of Chen et al.; US 2025/0056781 A1; 09/2023
Claim 8: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 1 ( as discussed above ).
Neither Chou nor Chen ( ‘244 ) nor Tsuchiaki appear to disclose a second gate structure spanning the first diffusion region and the third diffusion region to form the first pull-down transistor (PD1), wherein the first diffusion region is adjacent to and in direct contact with the third diffusion region.
However, Chen ( ‘781 ) teaches a second gate structure ( Fig. 4: bottom gate structure on left side ) spanning the first diffusion region ( Fig. 5: D1 ) and the third diffusion region ( Fig. 5: D5 ) to form the first pull-down transistor (PD1 ( as shown in Fig. 5 ), wherein the first diffusion region ( Fig. 5: D1 ) is adjacent to and in direct contact ( as shown in Fig. 5 ) with the third diffusion region ( Fig. 5: D5 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen (‘781 ) with Chou, Chen (‘244 ), and Tsuchiaki to implement a second gate structure spanning the first diffusion region and the third diffusion region to form the first pull-down transistor (PD1), wherein the first diffusion region is adjacent to and in direct contact with the third diffusion region because this approach creates a shared-drain or shared-source configuration that significantly reduces the cell area and enhances layout density.
Claim 9: Chou, Chen (‘244), Tsuchiaki, and Chen (‘781) disclose the layout pattern of the SRAM according to claim 8 ( as discussed above).
Chou teaches the second diffusion region ( Fig. 3 #54B ) does not contact the third diffusion region ( Fig. 3 #54C ) directly ( as shown in Fig. 3 ).
Claim 10: Chou, Chen (‘244), Tsuchiaki, and Chen (‘781 ) disclose the layout pattern of the SRAM according to claim 8 ( as discussed above ).
Neither Chou nor Chen (‘244) nor Tsuchiaki appear to disclose the second gate structure spans the fourth diffusion region to form the first pull-up transistor (PU1).
However, Chen ( ‘781 ) discloses the second gate structure ( Fig. 5: G1 ) spans the fourth diffusion region ( Fig. 5: D6 ) to form the first pull-up transistor (PU1) ( Fig. 5 PU1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen (‘781 ) with Chou, Chen (‘244 ), and Tsuchiaki to implement the second gate structure spans the fourth diffusion region to form the first pull-up transistor (PU1) because this approach is used to create a cross-coupled inverter pair that is responsible for maintaining the memory state.
Claim 11: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 1 ( as discussed above).
Neither Chou nor Chen ( ‘244) nor Tsuchiaki appear to disclose the first diffusion region comprises a first conductivity type, and the second diffusion region, the third diffusion region and the fourth diffusion region comprise a second conductivity type.
However, Chen (‘781) teaches the first diffusion region ( Fig. 2: left most diffusion region ) comprises a first conductivity type ( as shown in Fig. 2 ) , and the second diffusion region ( Fig. 2: top diffusion region on the left side near the first diffusion region), the third diffusion region ( Fig. 2: bottom diffusion region on the left side near the first diffusion region ) and the fourth diffusion region ( Fig. 2: long strip on the right side of the first P+ region on the left of the figure ) comprise a second conductivity type ( as shown in Fig. 2 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen (‘781) with Chou, Chen (‘244 ), and Tsuchiaki to implement the first diffusion region comprises a first conductivity type, and the second diffusion region, the third diffusion region and the fourth diffusion region comprise a second conductivity type because PN junctions are essential for creating controlled, high-density structures that create potential barriers, regulate current flow, and reduce leakage.
Claims 16-17 are rejected under U.S.C. 103 as being unpatentable over Chou et al.; US 2021/0320109 A1; 04/2020 in view of Chen et al.; US 10,541,244 B1; 09/2018 and further in view of Tsuchiaki; US 2007/0246781 A1; 02/2007 as it relates to claim 15 above and further in view of Lu et al.; US 9401366 B1; 07/2015
Claim 16: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 15 ( as discussed above).
Neither Chou nor Chen ( ‘244 ) nor Tsuchiaki appear to disclose the first body contact, the second body contact and the word line contact are aligned with each other in the second direction.
However, Lu teaches the first body contact ( Fig. 1: PG1A connection) , the second body contact ( Fig. 1: PG2A connection ) and the word line contact ( Fig. 1: WL ) are aligned with each other in the second direction ( as shown in Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lu with Chou, Chen (‘244 ), and Tsuchiaki to implement the first body contact, the second body contact and the word line contact are aligned with each other in the second direction because this maximizes integration density. Simplifies manufacturing, and improves device reliability.
Claim 17: Chou, Chen ( ‘244 ), and Tsuchiaki disclose the layout pattern of the SRAM according to claim 12 ( as discussed above).
Neither Chou nor Chen ( ‘244 ) nor Tsuchiaki appear to disclose the word line contact and the first part are not aligned in the first direction.
However, Lu teaches the word line contact ( Fig. 1: WL ) and the first part ( Fig. 1: #40 with PG1A connection ) are not aligned in the first direction ( as shown in Fig. 1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lu with Chou, Chen (‘244 ), and Tsuchiaki to implement the word line contact and the first part are not aligned in the first direction because this approach accommodates manufacturing constraints, minimizes noise, and manages layout density.
Allowable Subject Matter
Claims 4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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