CTNF 18/398,437 CTNF 99528 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Election/Restrictions 08-25-02 Applicant’s election of Group I, Species I in the reply filed on 04/08/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Group I, Species I and Group II are withdrawn. Claims 8, 10, and 18-20 are canceled. Claims 21-25 are new. Information Disclosure Statement The information disclosure statement (IDS) filed on 06/16/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner. Claim Objections 07-29-01 AIA Claim 17 is objected to because of the following informalities: In claim 17, line 6, “a first backside via-connector conductively connected” should read --a first third backside via-connector conductively connected-- and line 7 “the first backside power rail and the second backside power rail” should read --the first backside power rail and or the second backside power rail-- (emphasis added) . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-7, 9, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. (US 2022/0199608; hereinafter ‘Peng’) in view of Wu et al. (US 2022/0130760; hereinafter ‘Wu’) . Regarding claim 1 , Peng teaches an integrated circuit (200A and 200B, FIGS. 2A and 2B, [0042]) comprising: a first-type active-region structure (130A, FIGS. 1A and 1B, [0034]) and a second-type active-region structure (130B) each extending in a first direction (X-direction, [0035-0036]); a first terminal-conductor (265A, [0043]) intersecting the first-type active-region structure (130A) at a source region (262A, [0036, 0043]) of a first-type transistor (P-type transistor, [0036]; hereinafter ‘PTr’); a second terminal-conductor (265C, [0043]) intersecting the second-type active-region structure (130B) at a source region (262C, [0035, 0043]) of a second-type transistor (N-type transistor, [0035]; hereinafter ‘NTr’); a first frontside power rail (170A, FIG. 1C, [0040]), and a second frontside power rail (170E) each extending in the first direction (X-direction, [0040]), in a frontside metal layer (M0, [0040]), which is above the first-type active-region structure (130A) and the second-type active-region structure (130B); a backside signal line (240B, [0043, 0047]) in a first backside metal layer (M-1 layer, [0043]); a first backside power rail (210A, [0043]) and a second backside power rail (210B), each extending in the first direction (the backside power rail BM extends in the X-direction, FIG. 1A, [0038, 0043]), in a second backside metal layer (a second backside metal layer including BM, FIG. 2A) below the first backside metal layer (M-1 layer); a first backside via-connector (260A, [0043]) conductively connected to the source region (262A) of the first-type transistor (PTr); a first extended via-connector (a first extended via connector including 240A and 250A, [0043]; hereinafter ‘EVC1’) directly connected between the first backside via-connector (260A) and the first backside power rail (210A, wherein EVC1 directly connected between 260A and 210A); a second backside via-connector (260C) conductively connected to the source region (262C) of the second-type transistor (NTr); and a second extended via-connector (a second extended via connector including 240C and 250C; hereinafter ‘EVC2’) directly connected between the second backside via-connector (260C) and the second backside power rail (210B, wherein EVC2 directly connected between 260C and 210B). Peng does not teach the integrated circuit comprising: a substrate including active-region structures; frontside metal rail configured as power rails; and a backside metal layer below the substrate. Wu teaches an integrated circuit (FIG. 3D, [0074, 0078]) comprising: a substrate (308, [0079]) including active-region structures (active regions are formed in semiconductor substrate, [0037]); frontside metal rail (M1, [0080]) configured as power rails (234, 334, and 344 are frontside power rail, [0069]); and a backside metal layer (BM0, [0079]) below the substrate (BM0 below 308). As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Peng to obtain and achieve the integrated circuit comprising: a substrate including active-region structures, frontside metal rail configured as power rails; and a backside metal layer below the substrate as claimed, because it provides frontside and backside power-distribution structures for integrated-circuit power delivery while reducing routing congestion [0029]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Peng due to above reason. Regarding claim 2 , Peng in view of Wu teaches the integrated circuit of claim 1, further comprising: a first frontside via-connector ( Peng : a first via contact in the VD layer, FIG. 2B, [0043, 0077]; hereinafter ‘VD1’) directly connected between the first terminal-conductor (265A) and the first frontside power rail (170A, VD1 electrically coupling the MD region and the M0 rail through a continuous conductive path); and a second frontside via-connector (a second via contact in the VD layer; hereinafter ‘VD2’) directly connected between the second terminal-conductor (265C) and the second frontside power rail (170E, wherein VD2 directly connected between the MD region and the M0 rail through a continuous conductive path). Regarding claim 3 , Peng in view of Wu teaches the integrated circuit of claim 1, further comprising: a third terminal-conductor ( Peng : 265B, FIG. 2B, [0043]) intersecting the first-type active-region structure or the second-type active-region structure (the first-type active-region structure, 130A, [0046]) at a drain region of a transistor (a drain region 262B of PTr); and a third backside via-connector (260B, FIG. 2B, [0043]) directly connected between the third terminal-conductor (265B) and the backside signal line (240B, wherein 260B directly connected between 265B and 240B through a continuous conductive path). Regarding claim 4 , Peng in view of Wu teaches the integrated circuit of claim 1, further comprising: a gate-conductor ( Peng : 220B, FIG. 2B, [0046]) intersecting the first-type active-region structure or the second-type active-region structure (the first-type active-region structure 130A, FIGS. 1A and 1B, [0036]) at a channel region of a transistor (a channel region of PTr formed beneath 220B between 262A and 262B); and a third backside via-connector (260B, [0046]) directly connected between the gate-conductor (220B) and the backside signal line (240B, wherein 260B directly connected between 220B and 240B through a continuous conductive path). Regarding claim 5 , Peng in view of Wu teaches the integrated circuit of claim 1, wherein the backside signal line ( Peng : 240B formed according to layout pattern 140B shown in the top plan view of FIG. 1A, [0038, 0043]) is a two-dimensional signal line (a two-dimensional backside signal line including portions extending in both the X-direction and Y-direction, FIG. 1A) having a first signal line segment (a first segment of 240B extending in the X direction) extending in the first direction (X-direction) and a second signal line segment (a second segment of 240B extending in the Y direction) extending in a second direction (Y-direction) which is perpendicular to the first direction (X-direction). Regarding claim 6 , Peng teaches an integrated circuit (200A and 200B, FIGS. 2A and 2B, [0042]) comprising: a first-type active-region structure (130A, FIGS. 1A and 1B, [0034]) and a second-type active-region structure (130B) each extending in a first direction (X-direction, [0035-0036]); a first frontside power rail (170A, FIG. 1C, [0040]) and a second frontside power rail (170E), each extending in the first direction (X-direction, [0040]), in a frontside metal layer (M0, [0040]) which is above the first-type active-region structure (130A) and the second-type active-region structure (130B); a backside signal line (240B, [0043, 0047]) in a first backside metal layer (M-1 layer, [0043]); a first backside power rail (210A, [0043]) and a second backside power rail (210B), each extending in the first direction (the backside power rail BM extends in the X-direction, FIG. 1A, [0038, 0043]), in a second backside metal layer (a second backside metal layer including BM, FIG. 2A) below the first backside metal layer (M-1 layer); a first-type transistor (P-type transistor, [0036]; hereinafter ‘PTr’) having a source region (262A, [0036, 0043]) in the first-type active-region structure (130A) conductively connected to the first backside power rail (210A) through one or more via-connectors (240A, 250A, and 260A, [0043]); and a second-type transistor (N-type transistor, [0035]; hereinafter ‘NTr’) having a source region (262C, [0035, 0043]) in the second-type active-region structure (130B) conductively connected to the second backside power rail (210B) through one or more via-connectors (240C, 250C, and 260C). Peng does not teach the integrated circuit comprising: a substrate including active-region structures; frontside metal rail configured as power rails; and a backside metal layer below the substrate. Wu teaches an integrated circuit (FIG. 3D, [0074, 0078]) comprising: a substrate (308, [0079]) including active-region structures (active regions are formed in semiconductor substrate, [0037]); frontside metal rail (M1, [0080]) configured as power rails (234, 334, and 344 are frontside power rail, [0069]); and a backside metal layer (BM0, [0079]) below the substrate (BM0 below 308). As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Peng to obtain and achieve the integrated circuit comprising: a substrate including active-region structures, frontside metal rail configured as power rails; and a backside metal layer below the substrate as claimed, because it provides frontside and backside power-distribution structures for integrated-circuit power delivery while reducing power-rail congestion [0029]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Peng due to above reason. Regarding claim 7 , Peng in view of Wu teaches the integrated circuit of claim 6, further comprising: a first backside via-connector ( Peng : 260A, [0043]) conductively connected to the source region (262A) of the first-type transistor (PTr); a first extended via-connector (a first extended via connector including 240A and 250A, [0043]; hereinafter ‘EVC1’) directly connected between the first backside via-connector (260A) and the first backside power rail (210A, wherein EVC1 directly connected between 260A and 210A); a second backside via-connector (260C) conductively connected to the source region (262C) of the second-type transistor (NTr); and a second extended via-connector (a second extended via connector including 240C and 250C; hereinafter ‘EVC2’) directly connected between the second backside via-connector (260C) and the second backside power rail (210B, wherein EVC2 directly connected between 260C and 210B). Regarding claim 9 , Peng in view of Wu teaches the integrated circuit of claim 6, further comprising a single-stage cell ( Peng : PTr and NTr coupled to each other to form an inverter, [0036]; hereinafter ‘SSC’), wherein the single-stage cell is a buffer cell, an inverter cell, a NAND cell, a NOR cell, an AND cell, or an OR cell (SSC is the inverter cell). Regarding claim 21 , Peng in view of Wu teaches the integrated circuit of claim 9, wherein the single-stage cell ( Peng : SSC inverter cell including PTr and NTr coupled to each other, [0036]) comprises: a second first-type transistor (another P-type transistor in the repeated inverter-cell architecture, [0036]; hereinafter ‘PTr2’) having a source region (262A, [0036, 0043]), in the first-type active-region structure (130A), which is conductively connected to the first frontside power rail (170A, wherein 262A of PTr2 is conductively connected to 170A through MD region 265A and via contacts in VD layer, FIGS. 1C, 2A, and 2B, [0040, 0043, 0077]); a first backside power line (240A, FIGS. 2A and 2B, [0043]), in the first backside metal layer (M-1 layer), which is conductively connected to the source region (262A) of the second first-type transistor (PTr2, wherein 240A is conductively connected to 262A through 260A); a second second-type transistor (another N-type transistor in the repeated inverter-cell architecture; hereinafter ‘NTr2’) having a source region (262C, [0035, 0043]), in the second-type active-region structure (130B), which is conductively connected to the second frontside power rail (170E, wherein 262C of NTr2 is conductively connected to 170E through MD region 265C and via contacts in VD layer); and a second backside power line (240C, [0043]), in the first backside metal layer (M-1 layer), which is conductively connected to the source region (262C) of the second second-type transistor (NTr2, wherein 240C is conductively connected to 262C through 260C). Regarding claim 22 , Peng in view of Wu teaches the integrated circuit of claim 21, further comprising a first backside via-connector ( Peng : 260A, FIGS. 2A and 2B, [0043]) conductively connecting the first backside power line (240A) with the source region (262A) of the second first-type transistor (PTr2); and a second backside via-connector (260C, [0043]) conductively connecting the second backside power line (240C) with the source region (262C) of the second second-type transistor (NTr2). Regarding claim 23 , Peng teaches an integrated circuit (200A and 200B, FIGS. 2A and 2B, [0042]) comprising: a first-type active-region structure (130A, FIGS. 1A and 1B, [0034]) and a second-type active-region structure (130B) each extending in a first direction (X-direction, [0035-0036]); a first terminal-conductor (265A, [0043]) intersecting the first-type active-region structure (130A) at a source region (262A, [0036, 0043]) of a first-type transistor (P-type transistor, [0036]; hereinafter ‘PTr’); a second terminal-conductor (265C, [0043]) intersecting the second-type active-region structure (130B) at a source region (262C, [0035, 0043]) of a second-type transistor (N-type transistor, [0035]; hereinafter ‘NTr’); a first frontside power rail (170A, FIG. 1C, [0040]) and a second frontside power rail (170E), each extending in the first direction (X-direction, [0040]), in a frontside metal layer (M0, [0040]) which is above the first-type active-region structure (130A) and the second-type active-region structure (130B); a backside signal line (240B, [0043, 0047]) in a first backside metal layer (M-1 layer, [0043]); a first backside power rail (210A, [0043]) and a second backside power rail (210B), each extending in the first direction (the backside power rail BM extends in the X-direction, FIG. 1A, [0038, 0043]), in a second backside metal layer (a second backside metal layer including BM, FIG. 2A) below the first backside metal layer (M-1 layer); a first extended via-connector (a first extended via connector including 240A and 250A, [0043]; hereinafter ‘EVC1’) conductively connecting the first backside power rail (210A) to the source region (262A) of the first-type transistor (PTr, wherein EVC1 conductively connecting 210A to 262A of PTr); and a second extended via-connector (a second extended via connector including 240C and 250C; hereinafter ‘EVC2’) conductively connecting the second backside power rail (210B) to the source region (262C) of the second-type transistor (NTr, wherein EVC2 conductively connecting 210B to 262C of NTr). Peng does not teach the integrated circuit comprising: a substrate including active-region structures; frontside metal rail configured as power rails; and a backside metal layer below the substrate. Wu teaches an integrated circuit (FIG. 3D, [0074, 0078]) comprising: a substrate (308, [0079]) including active-region structures (active regions are formed in semiconductor substrate, [0037]); frontside metal rail (M1, [0080]) configured as power rails (234, 334, and 344 are frontside power rail, [0069]); and a backside metal layer (BM0, [0079]) below the substrate (BM0 below 308). As taught by Wu, one of ordinary skill in the art would utilize and modify the above teaching into Peng to obtain and achieve the integrated circuit comprising: a substrate including active-region structures, frontside metal rail configured as power rails; and a backside metal layer below the substrate as claimed, because it provides frontside and backside power-distribution structures for integrated-circuit power delivery while reducing routing congestion [0029]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wu in combination with Peng due to above reason. Regarding claim 24 , Peng in view of Wu teaches the integrated circuit of claim 23, further comprising: a first frontside via-connector ( Peng : a first via contact in the VD layer, FIG. 2B, [0043, 0077]; hereinafter ‘VD1’) directly connected between the first terminal-conductor (265A) and the first frontside power rail (170A, VD1 electrically coupling the MD region and the M0 rail through a continuous conductive path); and a second frontside via-connector (a second via contact in the VD layer; hereinafter ‘VD2’) directly connected between the second terminal-conductor (265C) and the second frontside power rail (170E, wherein VD2 directly connected between the MD region and the M0 rail through a continuous conductive path). Regarding claim 25 , Peng in view of Wu teaches the integrated circuit of claim 23, wherein the backside signal line ( Peng : 240B formed according to layout pattern 140B shown in the top plan view of FIG. 1A, [0038, 0043]) is a two-dimensional signal line (a two-dimensional backside signal line including portions extending in both the X-direction and Y-direction, FIG. 1A) having a first signal line segment (a first segment of 240B extending in the X direction) extending in the first direction (X-direction) and a second signal line segment (a second segment of 240B extending in the Y direction) extending in a second direction (Y-direction) which is perpendicular to the first direction (X-direction) . 07-21-aia AIA Claim s 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Peng (US 2022/0199608) in view of Wu (US 2022/0130760), and further in view of Iwahori (US 2022/0223588; hereinafter ‘Iwahori’) . Regarding claim 11 , Peng in view of Wu teaches the integrated circuit of claim 6, further comprising a power pickup cell ( Peng : a structure including 265A, VD, and 260A configured to provide a supply voltage from the power rail to the PTr, FIGS. 2A and 2B, [0039, 0043, 0077]; hereinafter ‘PPC’), and the power pickup cell (PPC) comprises: a first terminal-conductor (265A) intersecting the first-type active-region structure (130A); a first frontside via-connector (VD) directly connected between the first terminal-conductor (265A) and the first frontside power rail (170A, wherein VD directly connected between 265A and 170A through a continuous conductive path); and a first backside via-connector (260A) conductively connected between the first terminal-conductor (265A) and the first backside power rail (210A, wherein 260A connected between 265A and 210A through a continuous conductive path). Peng in view of Wu does not teach the integrated circuit comprising the power pickup cell, wherein the power pickup cell either contains no transistor or has each transistor therein implemented as a dummy transistor. Iwahori teaches an integrated circuit (FIG. 1, [0037]) comprising the power pickup cell (filler cell CF associated with local interconnects connected to buried power supply lines 11 and 12 supplying VDD and VSS as functional power pickup structures, [0044]), wherein the power pickup cell (CF) either contains no transistor or has each transistor therein implemented as a dummy transistor (CF does not include a nanosheet FET and has no logical function, corresponding to a dummy transistor structure, [0040-0041]). As taught by Iwahori, one of ordinary skill in the art would utilize and modify the above teaching into Peng in view of Wu to obtain and achieve the integrated circuit comprising the power pickup cell, wherein the power pickup cell either contains no transistor or has each transistor therein implemented as a dummy transistor as claimed, because it controls variations in transistor performance while improving reliability and yield of the semiconductor integrated circuit device [0010]. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Iwahori in combination with Peng in view of Wu due to above reason. Regarding claim 12 , Peng in view of Wu and Iwahori teaches the integrated circuit of claim 11, wherein the power pickup cell further comprises: a first backside conductor ( Peng : 240A, FIGS. 2A and 2B, [0043]) formed in the first backside metal layer (M-1 layer), wherein the first backside via-connector (260A) is conductively connected to the first backside power rail (210A) through the first backside conductor (240A, wherein 260A connected to 210A through 240A). Regarding claim 13 , Peng in view of Wu and Iwahori teaches the integrated circuit of claim 11, wherein the power pickup cell ( Peng : PPC) further comprises: a first extended via-connector (a first extended via connector including 240A and 250A, [0043]; hereinafter ‘EVC1’) directly connected between the first backside via-connector (260A) and the first backside power rail (210A, wherein EVC1 directly connected between 260A and 210A). Regarding claim 14 , Peng in view of Wu and Iwahori teaches the integrated circuit of claim 11, wherein the power pickup cell ( Peng : PPC) further comprises: a second terminal-conductor (265C, FIG. 2A, [0043]) intersecting the second-type active-region structure (130B); a second frontside via-connector (a second via contact in the VD layer, FIG. 2B, [0043, 0077]; hereinafter ‘VD2’) directly connected between the second terminal-conductor (265C) and the second frontside power rail (170E, wherein VD2 directly connected between the MD region and the M0 rail through a continuous conductive path); and a second backside via-connector (260C, [0043]) conductively connected between the second terminal-conductor (265C) and the second backside power rail (210B, wherein 260C connected between 265C and 210B). Regarding claim 15 , Peng in view of Wu and Iwahori teaches the integrated circuit of claim 11, Peng in view of Wu does not teach the integrated circuit wherein the power pickup cell has a first vertical cell boundary and a second vertical cell boundary extending in a second direction perpendicular to the first direction, and wherein each of the first vertical cell boundary and the second vertical cell boundary passes through a first boundary isolation region in the first-type active-region structure and a second boundary isolation region in the second-type active-region structure. Iwahori teaches the integrated circuit wherein the power pickup cell (CF, FIG. 1) has a first vertical cell boundary (the left side edge of CF; hereinafter ‘CFL’) and a second vertical cell boundary (the right side edge of CF; hereinafter ‘CFR’) extending in a second direction (Y-direction) perpendicular to the first direction (X-direction), and wherein each of the first vertical cell boundary (CFL) and the second vertical cell boundary (CFR) passes through a first boundary isolation region (32 and 35, [0063]) in the first-type active-region structure (the source/drain/channel regions associated with P1, [0047]) and a second boundary isolation region (34 and 36, [0063]) in the second-type active-region structure (the source/drain/channel regions associated with N1, [0047]). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Iwahori to obtain and achieve the integrated circuit wherein the power pickup cell has a first vertical cell boundary and a second vertical cell boundary extending in a second direction perpendicular to the first direction, and wherein each of the first vertical cell boundary and the second vertical cell boundary passes through a first boundary isolation region in the first-type active-region structure and a second boundary isolation region in the second-type active-region structure as claimed, because the boundary isolation structures reduce variations in transistor characteristics at cell boundaries while improving reliability and yield of the semiconductor integrated circuit device [0010]. Regarding claim 16 , Peng in view of Wu and Iwahori teaches the integrated circuit of claim 14, further comprising: a plurality of gate-conductors ( Peng : layout patterns 120A, 120B, 120C in FIGS. 1A-1C corresponding to gate structures 220A, 220B, 220C in FIG. 2B, [0046]; hereinafter ‘GC’) extending in a second direction (Y-direction, FIGS. 1A-1C, [0036]) below the frontside metal layer (M0). Peng in view of Wu does not teach the integrated circuit further comprising: two adjacent gate-conductors are separated by a pitch distance equal to a contacted poly pitch (“CPP”), and wherein the power pickup cell has a cell width that is equal to or less than four CPPs. Iwahori teaches the integrated circuit further comprising: two adjacent gate-conductors are separated by a pitch distance equal to a CPP, and wherein the power pickup cell has a cell width that is equal to or less than four CPPs (CF has a cell width extending across less than four adjacent gate-conductor pitches including 55, 51, 52, 56, FIG. 1, [0053]). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Iwahori to obtain and achieve the integrated circuit further comprising: two adjacent gate-conductors are separated by a pitch distance equal to a CPP, and wherein the power pickup cell has a cell width that is equal to or less than four CPPs as claimed, because the compact boundary filler-cell structure arranged within adjacent gate-conductor pitches reduce variation in transistor characteristics while improving reliability and yield of the semiconductor integrated circuit device [0010]. Regarding claim 17 , Peng in view of Wu and Iwahori teaches the integrated circuit of claim 16, the power pickup cell ( Peng : PPC) further comprises: a third terminal-conductor (265B, FIG. 2B, [0043]) intersecting one of the first-type active-region structure or the second-type active-region structure (the drain region 262B of 130A, [0046]); a third frontside via-connector (275, [0043]) directly connecting the third terminal-conductor (265B) with one of the first frontside power rail or the second frontside power rail (270 corresponding to 170A, wherein 275 directly connecting 265B and 270); and a first backside via-connector (260B, [0043]) conductively connected between the third terminal-conductor (265B, wherein 260B connected between 265B). Peng in view of Iwahori does not teach that a third backside via-connector associated with a drain region conductively connected to one of the first backside power rail and the second backside power rail. Wu teaches the integrated circuit further comprising a third backside via-connector (SG, FIGS. 10A and 10B, [0122]) associated with a drain region (drain region 1012, 1016, 1020) conductively connected to one of the first backside power rail and the second backside power rail (SG conductively connected to back power rail 348’). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Wu to obtain and achieve the integrated circuit further comprising a third backside via-connector associated with a drain region conductively connected to one of the first backside power rail and the second backside power rail as claimed, because using similar backside routing structures for source/drain regions reduces routing congestion and improves backside power distribution [0029]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JIYOUNG OH/Examiner, Art Unit 2818 /DUY T NGUYEN/ Primary Examiner, Art Unit 2818 6/11/26 Application/Control Number: 18/398,437 Page 2 Art Unit: 2818 Application/Control Number: 18/398,437 Page 3 Art Unit: 2818 Application/Control Number: 18/398,437 Page 4 Art Unit: 2818 Application/Control Number: 18/398,437 Page 5 Art Unit: 2818 Application/Control Number: 18/398,437 Page 6 Art Unit: 2818 Application/Control Number: 18/398,437 Page 7 Art Unit: 2818 Application/Control Number: 18/398,437 Page 8 Art Unit: 2818 Application/Control Number: 18/398,437 Page 9 Art Unit: 2818 Application/Control Number: 18/398,437 Page 10 Art Unit: 2818 Application/Control Number: 18/398,437 Page 11 Art Unit: 2818 Application/Control Number: 18/398,437 Page 12 Art Unit: 2818 Application/Control Number: 18/398,437 Page 13 Art Unit: 2818 Application/Control Number: 18/398,437 Page 14 Art Unit: 2818 Application/Control Number: 18/398,437 Page 15 Art Unit: 2818 Application/Control Number: 18/398,437 Page 16 Art Unit: 2818 Application/Control Number: 18/398,437 Page 17 Art Unit: 2818 Application/Control Number: 18/398,437 Page 18 Art Unit: 2818 Application/Control Number: 18/398,437 Page 19 Art Unit: 2818
Prosecution Insights