DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-7, 10-11, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Patent No. 10,332,916).
Regarding to claim 1, Lee teaches a display device (column 6, lines 36-37) comprising:
an active layer disposed on a substrate (Fig. 5, element 30; column 6, lines 13-14); and
a conductive pattern (Fig. 5, element 50; column 6, lines 52-54; Fig. 1, element 200; column 3, line 27) disposed on or under the active layer and including:
an upper conductive layer having a first line width in a direction (Fig. 5, element 52b; column 6, lines 55-56; Fig. 1, element 220b; column 3, line 45, the direction is direction into the page); and
a lower conductive layer including:
a first metal layer disposed under the upper conductive layer (Fig. 5, element 51; column 6, lines 53-54; Fig. 1, element 210; column 3, line 51-52); and
a capping layer disposed between the upper conductive layer and the first metal layer (Fig. 5, element 52a; column 6, line 55; Fig. 1, element 220a; column 3, line 46) and having a second line width in the direction greater than the first line width (Fig. 3, Fig. 5, capping layer 220a/52a having second line width in the direction greater than the first line width of metal layer 220b/52b).
Regarding to claim 6, Lee teaches the capping layer includes a titanium alloy (column 4, lines 65-67).
Regarding to claim 7, Lee teaches the capping layer includes titanium nitride (column 4, lines 65-67).
Regarding to claim 10, Lee teaches an insulating layer disposed between the active layer and the conductive pattern, wherein the active layer and the conductive pattern are spaced apart from each other by the insulating layer (Fig. 5, element 40, column 6, line 14).
Regarding to claim 11, Lee teaches a method of manufacturing a display device, the method comprising:
forming an active layer on a substrate (Fig. 10, element 100); and
forming a conductive pattern on or under the active layer (Fig. 11, element 202), wherein the forming of the conductive pattern includes:
forming a preliminary lower conductive layer including a first preliminary metal layer (Fig. 10, element 1; column 8, line 26) and a preliminary capping layer disposed on the first preliminary metal layer (Fig. 10, element 2; column 8, line 45)
forming a preliminary upper conductive layer on the preliminary lower conductive layer (Fig. 10, element 3; column 8, lines 29-30);
forming an upper conductive layer having a first line width in a direction by patterning the preliminary upper conductive layer (Fig. 11, forming upper conductive layer 222b having a first line width in a direction by patterning the preliminary upper conductive layer 3); and
forming a lower conductive layer including a first metal layer disposed under the upper conductive layer and a capping layer disposed between the upper conductive layer and the first metal layer and having a second line width in the direction greater than the first line width by patterning the preliminary lower conductive layer (Fig. 11, forming lower conductive layer including first metal layer 210 disposed under the upper conductive layer 222b, and capping layer 222a disposed between the upper conductive layer 222b and the first metal layer 210 and having a second line width in the direction greater than the first line width of the upper conductive layer 222b by patterning the preliminary lower conductive layer (which including the first preliminary metal layer 1 and the preliminary capping layer 2)).
Regarding to claim 16, Lee teaches the preliminary capping layer includes a titanium alloy (column 8, line 45).
Claims 11 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (U.S. Patent No. 10,332,916) (other layers are mapped for meeting limitations of claims 18-19).
Regarding to claim 11, Lee teaches a method of manufacturing a display device, the method comprising:
forming an active layer on a substrate (Fig. 10, element 100); and
forming a conductive pattern on or under the active layer (Fig. 11, element 202), wherein the forming of the conductive pattern includes:
forming a preliminary lower conductive layer including a first preliminary metal layer (Fig. 10, element 2) and a preliminary capping layer disposed on the first preliminary metal layer (Fig. 10, element 3);
forming a preliminary upper conductive layer on the preliminary lower conductive layer (Fig. 10, element 4);
forming an upper conductive layer having a first line width in a direction by patterning the preliminary upper conductive layer (Fig. 11, forming upper conductive layer 222c having a first line width in a direction by patterning the preliminary upper conductive layer 4); and
forming a lower conductive layer including a first metal layer disposed under the upper conductive layer and a capping layer disposed between the upper conductive layer and the first metal layer and having a second line width in the direction greater than the first line width by patterning the preliminary lower conductive layer (Fig. 11, forming lower conductive layer including first metal layer 222a disposed under the upper conductive layer 222c, and capping layer 222b disposed between the upper conductive layer 222c and the first metal layer 222a and having a second line width in the direction greater than the first line width of the upper conductive layer 222c by patterning the preliminary lower conductive layer (which including the first preliminary metal layer 2 and the preliminary capping layer 3)).
Regarding to claim 18, Lee teaches
the preliminary lower conductive layer further includes a second preliminary metal layer disposed (Fig. 10, element 1) under the first preliminary metal layer (Fig. 10, element 2), and
the lower conductive layer further includes a second metal layer disposed under the first metal layer after the forming of the lower conductive layer (Fig. 11, the lower conductive layer further includes second metal layer 210 disposed under the first metal layer 222a after the forming of the lower conductive layer).
Regarding to claim 19, Lee teaches the second preliminary metal layer includes titanium (column 8, lines 45).
Claims 1-3, 8, 11, 15, 18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yaegashi et al. (U.S. Patent No. 6,376,861).
Regarding to claim 1, Lee teaches a display device comprising:
an active layer disposed on a substrate (Fig. 1, element 22; column 5, lines 31-32); and
a conductive pattern (Fig. 1, element 36a; column 5, lines 41-42) disposed on or under the active layer and including:
an upper conductive layer having a first line width in a direction (Fig. 1, element 34; column 5, line 41, the direction is direction into the page); and
a lower conductive layer including:
a first metal layer disposed under the upper conductive layer (Fig. 1, element 30; column 5, line 35); and
a capping layer disposed between the upper conductive layer and the first metal layer (Fig. 1, element 32; column 5, lines 40-41) and having a second line width in the direction greater than the first line width (Fig. 1, capping layer 32 having line width greater than the line width of metal layer 34).
Regarding to claim 2, Yaegashi teaches a side surface of the conductive pattern has a step (Fig. 1, Fig. 5A),
Regarding to claim 3, Yaegashi teaches the upper conductive layer includes copper, and the first metal layer includes aluminum (column 9, line 8).
Regarding to claim 8, Yaegashi teaches the lower conductive layer further includes a second metal layer disposed under the first metal layer (Fig. 1, element 28).
Regarding to claim 11, Yaegashi teaches a method of manufacturing a display device, the method comprising:
forming an active layer on a substrate (Fig. 5C, element 22; column 5, lines 31-32); and
forming a conductive pattern on or under the active layer (Fig. 5C, element 36a; column 5, lines 41-42), wherein the forming of the conductive pattern includes:
forming a preliminary lower conductive layer including a first preliminary metal layer (Fig. 4C, element 30; column 5, line 35) and a preliminary capping layer disposed on the first preliminary metal layer (Fig. 4C, element 32; column 5, lines 37);
forming a preliminary upper conductive layer on the preliminary lower conductive layer (Fig. 4C, element 34; column 5, line 41);
forming an upper conductive layer having a first line width in a direction by patterning the preliminary upper conductive layer (Fig. 5A, upper conductive layer 34 having a first line width in a direction formed by patterning the preliminary upper conductive layer); and
forming a lower conductive layer including a first metal layer disposed under the upper conductive layer and a capping layer disposed between the upper conductive layer and the first metal layer and having a second line width in the direction greater than the first line width by patterning the preliminary lower conductive layer (Fig. 5C, lower conductive layer including a first metal layer 30 disposed under the upper conductive layer 34 and a capping layer 32 disposed between the upper conductive layer and the first metal layer and having a second line width in the direction greater than the first line width formed by patterning the preliminary lower conductive layer).
Regarding to claim 15, Yaegashi teaches the preliminary upper conductive layer includes copper, and the first preliminary metal layer includes aluminum (column 9, line 8).
Regarding to claim 18, Yaegashi teaches
the preliminary lower conductive layer further includes a second preliminary metal layer disposed (Fig. 4C, element 28) under the first preliminary metal layer (Fig. 4C, element 30), and
the lower conductive layer further includes a second metal layer disposed under the first metal layer after the forming of the lower conductive layer (Fig. 5C, the lower conductive layer further includes second metal layer 28 disposed under the first metal layer 30 after the forming of the lower conductive layer).
Regarding to claim 20, Yaegashi teaches after the forming of the conductive pattern, a side surface of the conductive pattern has a step (Figs. 5A-B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yaegashi et al. (U.S. Patent No. 6,376,861), as applied to claim 1 above.
Regarding to claim 4, Yaegashi discloses a difference between the second line width and the first line width (Fig. 1). Yaegashi is silent as to a range, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a difference between the second line width and the first line width to be in a range of about 0.3 micrometers to about 0.9 micrometers in order to increase stability, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 5, Yaegashi discloses a thickness of the upper conductive layer and a thickness of the lower conductive layer (Fig. 1). Yaegashi is silent as to a range, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the upper conductive layer to be in a range of about 1500 A to about 3000A and a thickness of the lower conductive layer to be in a range of about 1500 A to about 3000 A in order to obtain desired conductivity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yaegashi et al. (U.S. Patent No. 6,376,861), as applied to claim 11 above.
Regarding to claim 17, Yaegashi discloses a difference between the second line width and the first line width (Fig. 1). Yaegashi is silent as to a range, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a difference between the second line width and the first line width to be in a range of about 0.3 micrometers to about 0.9 micrometers in order to increase stability, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claims 9 and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 9, the prior art fails to anticipate or render obvious the claimed limitations including “the second metal layer includes titanium” in combination with the limitation recited in claim 1 and claim 8.
Regarding to claim 12, the prior art fails to anticipate or render obvious the claimed limitations including “the forming of the upper conductive layer includes etching a portion of the preliminary upper conductive layer through a wet etching process and the forming of the lower conductive layer includes etching a portion of the preliminary lower conductive layer through a dry etching process” in combination with the limitation recited in claim 11.
Pertinent Art
For the benefits of the Applicant, US-20220181411-A1, US-11158693-B2, US-8129724-B2, US-11164932-B2, US-20240276801-A1, US-7929341-B2, US-11050045-B2, US-20220229322-A1, US-9640642-B2, are US-7371621-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose the combination of limitations including “forming a lower conductive layer including a first metal layer disposed under the upper conductive layer and a capping layer disposed between the upper conductive layer and the first metal layer and having a second line width in the direction greater than the first line width by patterning the preliminary lower conductive layer, wherein the forming of the upper conductive layer includes etching a portion of the preliminary upper conductive layer through a wet etching process, and the forming of the lower conductive layer includes etching a portion of the preliminary lower conductive layer through a dry etching process”.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897