DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
2. Applicant’s election without traverse of Invention I, directed to a device, the device Species I-1 shown in Figs. 2-3 in the Response to Restriction Requirements filed 04/01/26 has been acknowledged. Applicant withdraw from consideration Claims 6-7, 13-14 directed to species of Invention I not chosen for examination, and cancelled Claims 17-20 directed to Invention II (method claims), amended device Claims 4 and 9, added new device Claims 21-24, and stated that Claims 1-5, 8-12, 15-16, and 21-24 belong to Species I-1.
Status of Claims
3. Claims 6-7, 13-14 are withdrawn from further consideration as being drawn to non-elected inventions.
Claims 1-5, 8-12, 15-16, and 21-24 are examined on merits herein.
Claim Rejections - 35 USC § 112
4. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
5. Claims 21-24 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
6. In re Claim 21: New Claim 21 recites: “wherein a portion of the channel layer wraps around a sidewall of the gate electrode”. However, the specification does not teach such portion of the channel layer wraps around a sidewall of the gate electrode. Accordingly, the combination of recitations represents a new matter. Appropriate correction is required.
7. In re Claims 22-24: Claims 22-24 are rejected under 35 U.S.C. 112(a) due to dependency on Claim 21.
Double Patenting
8. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based e-Terminal Disclaimer may be filled out completely online using web-screens. An e-Terminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about e-Terminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
9. Claim 1 is provisionally rejected on the ground of non-statutory double patenting as being unpatentable over Claim 1 of co-pending Application No. 18/398,882. Although the claims at issue are not identical, they are not patentably distinct from each other because a recitation of Claim 1 of 18/398,882: recites “the channel layer is included on at least two sides of the gate electrode and under a bottom surface of the gate electrode” that includes such limitation of Claim 1 of the current application: “the channel layer surrounds a perimeter of the gate electrode”, while all other limitations are the same.
This is a provisional non-statutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1-5, 9-12, 15, 16, 21-24, is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 2023/0200084) in view of Atanasov et al. (US 2022/0189957).
In re Claims 1, 21, Sharma teaches a semiconductor device, comprising (Fig. 8A):
-a dielectric layer 312 (paragraph 0058); and
-and a memory cell structure (item 800, [0088]), in dielectric layers, comprising:
-a storage structure (item 820, [0088]);
-and a transistor structure (item 320, [0088]), above the storage structure, comprising:
-a first source/drain region (item 308-1, [0061]);
-a second source/drain region (item 308-2, [0061]) above the first source/drain region;
-a gate electrode (item 304, [0058]) that extends between the first source/drain region and the second source/drain region;
-and a channel layer (item 306, [0069]) that extends between the first source/drain region and the second source/drain region, wherein the channel layer surrounds a perimeter of the gate electrode (this limitation would read through the structure of fig. 8A, items 308-1, 308-2, 316-1 and 316-2).
Sharma does not teach that the dielectric layer presents a plurality of backend dielectric layers, where the memory cell structure is in the plurality of backed dielectric layers. However, Examiner notes that in semiconductor manufacturing, backend dielectric layers are insulating layers deposited during the back-end-of-line (BEOL) process to separate and protect conductive metal interconnects.
Atanasov teaches (Fig. 1, paragraph 0016) a memory cell structure 102 being disposed in a plurality of backend dielectric layers 116 and 118. Therefore, Sharma and Atanasov teach analogous arts directed to a memory cell structure being a stack of a transistor and a storage device disposed within an opening of a dielectric materials, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sharma device in view of the Atanasov device, since they are from the same field of endeavor, and Atanasov created a memory device that successfully functions.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sharma structure by substituting its single dielectric layer with a plurality of backend dielectric layers (per Atanasov), creating by that a structure in which the memory cell structure would be disposed in the plurality of backend dielectric layers, when such dielectric layer is preferred by the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 9, Sharma teaches a semiconductor device, comprising (Fig. 8A):
-a storage structure (item 820, [0088]);
-a first source/drain region (item 308-1, [0061]);
-a gate electrode (item 304, [0058]) having an elongated shape in a direction that is approximately perpendicular to a dielectric layer 312 (paragraph 0058);
-wherein the first source/drain region (item 308-1, [0061]) is located under a bottom surface of the gate electrode;
-a channel layer (item 306, [0069]) that wraps around a sidewall and the bottom surface of the gate electrode (this limitation would read through the structure of fig. 8A, items 308-1, 308-2, 316-1 and 316-2);
-and a second source/drain region (item 308-2, [0061]) above the first source/drain region and adjacent to the sidewall of the channel layer, wherein the gate electrode is adjacent to the second source/drain region.
Sharma does not teach that the dielectric layer presents a plurality of backend dielectric layers, where the memory cell structure is in the plurality of backed dielectric layers. However, Examiner notes that in semiconductor manufacturing, backend dielectric layers are insulating layers deposited during the back-end-of-line (BEOL) process to separate and protect conductive metal interconnects.
Atanasov teaches (Fig. 1, paragraph 0016) a memory cell structure 102 being disposed in a plurality of backend dielectric layers 116 and 118. Therefore, Sharma and Atanasov teach analogous arts directed to a memory cell structure being a stack of a transistor and a storage device disposed within an opening of a dielectric materials, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sharma device in view of the Atanasov device, since they are from the same field of endeavor, and Atanasov created a memory device that successfully functions.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sharma structure by substituting its single dielectric layer with a plurality of backend dielectric layers (per Atanasov), creating by that a structure in which the memory cell structure would be disposed in the plurality of backend dielectric layers, when such dielectric layer is preferred by the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 2, Sharma/Atanasov teaches the semiconductor device of claim 1, wherein a first portion of the channel layer surrounds the perimeter of the gate electrode; and wherein a second portion of the channel layer is on the second source/drain region (this limitation would read through the structure fig. 8A of Sharma, items 308-1, 308-2, 316-1 and 316-2).
In re Claim 3, Sharma/Atanasov teaches the semiconductor device of claim 2, wherein the first portion of the channel layer is located along a side of the second source/drain region (this limitation would read through the structure fig. 8A of Sharma, items 308-1, 308-2, 316-1 and 316-2).
In re Claim 4, Sharma/Atanasov teaches the semiconductor device of claim 2, wherein the first portion of the channel layer is included under a bottom surface of the gate electrode; and wherein the first portion of the channel layer is located between the first source/drain region and the bottom surface of the gate electrode (this limitation would read through the structure fig. 8A of Sharma, items 308-1, 308-2, 316-1 and 316-2, 822-1, 822-2, 304).
In re Claim 5, Sharma/Atanasov teaches the semiconductor device of claim 1, further comprising: a gate dielectric layer that extends between the first source/drain region and the second source/drain region, wherein the gate dielectric layer surrounds the perimeter of the gate electrode (this limitation would read through the structure fig. 8A of Sharma, items 308-1, 308-2, 316-1 and 316-2, 822-1, 822-2, 304).
In re Claim 8, Sharma/Atanasov teaches the semiconductor device of claim 1, wherein the channel layer comprises a metal-oxide semiconductor material (this limitation would read through [0063] of Sharma, wherein is disclosed the channel material 306 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide); and
wherein the semiconductor device further comprises: one or more diffusion barrier layers between the first source/drain region and the second source/drain region (this limitation would read through [0062] of Sharma, wherein is disclosed further layers may be included next to a gate electrode material 304 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer).
In re Claims 10-12, 15, 16, Sharma/Atanasov teaches the semiconductor device of claim 9, wherein a first portion of the channel layer wraps around the sidewall and the bottom surface of the gate electrode, and wherein a second portion of the channel layer extends in a direction that is approximately parallel with the dielectric layer, as explained above.
Sharma does not teach that the dielectric layer presents a plurality of backend dielectric layers, where the memory cell structure is in the plurality of backed dielectric layers. However, Examiner notes that in semiconductor manufacturing, backend dielectric layers are insulating layers deposited during the back-end-of-line (BEOL) process to separate and protect conductive metal interconnects. Atanasov teaches (Fig. 1, paragraph 0016) a memory cell structure 102 being disposed in a plurality of backend dielectric layers 116 and 118. Therefore, Sharma and Atanasov teach analogous arts directed to a memory cell structure being a stack of a transistor and a storage device disposed within an opening of a dielectric materials, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Sharma device in view of the Atanasov device, since they are from the same field of endeavor, and Atanasov created a memory device that successfully functions.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Sharma structure by substituting its single dielectric layer with a plurality of backend dielectric layers (per Atanasov), creating by that a structure in which the memory cell structure would be disposed in the plurality of backend dielectric layers, when such dielectric layer is preferred by the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 22, Sharma/Atanasov teaches the semiconductor device of claim 21, wherein the gate electrode and the portion of the channel layer have an approximately cylindrical shape (this limitation would read through [0037] of Atanasov wherein is disclosed the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate).
In re Claim 23, Sharma/Atanasov teaches the semiconductor device of claim 21, wherein an additional portion of the channel layer is on the second source/drain region (this limitation would read through [0034] of Atanasov wherein is disclosed the device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620).
In re Claim 24, Sharma/Atanasov teaches the semiconductor device of claim 21, wherein the first source/drain region is electrically connected to the storage structure (this limitation would read through [0078] of Sharma wherein is disclosed each individual bitline 340 still extends, along a respective longitudinal axis 410-i, as an electrically continuous conductive structure to wrap around all of the second S/D regions 308-2 of the different transistors 320).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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