Prosecution Insights
Last updated: October 01, 2026
Application No. 18/398,937

PHOTONICS DEVICE WITH BACKSIDE TRANSMISSIVE REGION

Non-Final OA §102§103§112
Filed
Dec 28, 2023
Examiner
HAN, JONATHAN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1078 granted / 1287 resolved
+15.8% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
23 currently pending
Career history
1303
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
55.6%
+15.6% vs TC avg
§102
31.9%
-8.1% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1287 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention II (Claims 10-15) and new claims 21-34 in the reply filed on 08/05/2026 is acknowledged. Claim Rejections - 35 USC § 112 Claim 10-15 and 21-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites the limitation "the trench structure" in line 7. There is insufficient antecedent basis for this limitation in the claim. It appears that Applicant intended to reference “a vertically-arranged trench structure” in line 3, however “vertically-arrange” is not present within the language of the limitation of “the trench structure.” Examiner encourages amendment to either remove “vertically-arranged” from the first introduction of “a vertically-arranged trench” to fix antecedent issue or reintroduce “vertically-arranged” into all instances of “the trench structure” in subsequent claims. It appears however that “vertically-arranged” is unnecessary to the scope of the claim. Clarification is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 10, 12-14, 21, 26, 28-34 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Budd et al. (U.S. Publication No. 2007/0085215 A1; hereinafter Budd) With respect to claim 10, Budd discloses a method, comprising: forming a photodiode structure in a first semiconductor device [47] (See ¶[0047]); forming a transmissive region including a vertically-arranged trench structure [40] in a second semiconductor device [41], wherein the transmissive region is transmissive to light waves (see Figure 4dl); and joining the first semiconductor device and the second semiconductor device along a bond line to locate the transmissive region including the vertically-arranged trench structure below the photodiode structure (see Figure 4dl). With respect to claim 12, Budd discloses wherein forming the transmissive region including the vertically-arranged trench structure in the second semiconductor device comprises: forming a cavity [10] in a dielectric layer [11] (see ¶[0019]; dielectric materials can be used to form the substrate), and forming a reflector structure [12/14] within the cavity (see ¶[0020-0021]; “When a low index of refraction material is adjacent to a relatively high index of refraction material, light approaching the interface from the higher index material side intersecting the interface under the critical angle is internally reflected as defined by Snell's Law.”). With respect to claim 13, Budd discloses wherein forming the transmissive region including the vertically-arranged trench structure further comprises: forming a micro-lens structure [102] on a substrate layer [101] exposed at a bottom of the cavity (see Figure 10d). With respect to claim 14, Budd discloses wherein forming the reflector structure within the cavity comprises: forming one or more conformal layers of the reflector structure on surfaces of the dielectric layer and the cavity, and removing a portion of the one or more conformal layers from a bottom surface of the cavity (see Figures 5f-5I). With respect to claim 21, Budd discloses wherein the trench structure is arranged in a direction that is orthogonal to the bond line, and wherein the trench structure is configured to transmit light waves into the first semiconductor device for propagation to the photodiode structure (see Figure 1d) With respect to claim 26, Budd discloses wherein the trench structure is a first trench structure [70] arranged in a first direction that is orthogonal to the bond line, wherein the light waves are first light waves, wherein the transmissive region includes a second trench structure [70] adjacent to the first trench structure, wherein the second trench structure is arranged in a second direction that is orthogonal to the bond line, and wherein the second trench structure is configured to transmit second light waves into the first semiconductor device for propagation to the photodiode structure (see Figure 7e) With respect to claim 28, Budd discloses wherein the first trench structure penetrates into the second semiconductor device a first height, and wherein the second trench structure penetrates into the second semiconductor device a second height that is a same approximate height as the first height (See Figure 7e) With respect to claim 29, Budd discloses wherein the first light waves correspond to light waves of a first wavelength and the second light waves correspond to light waves of a second wavelength (see Figure 7e and ¶[0042]; note that no language disallows both the first and second wavelength being the same wavelength). With respect to claim 30, Budd discloses wherein the transmissive region is arranged to receive the light waves through the trench structure in the second semiconductor device; and wherein the trench structure is configured to transfer the light waves to the photodiode structure (See Figure 1d). With respect to claim 31, Budd discloses wherein the light waves are unimpeded by structures within the trench structure (See Figure 1d) With respect to claim 32, Budd discloses wherein forming the transmissive region comprises: forming a micro-lens structure [102] in the trench structure, wherein the micro-lens structure is arranged to focus the light waves in the trench structure (See Figure 10a and 10d). With respect to claim 33, Budd discloses providing a waveguide structure that is arranged to propagate the light waves in the first semiconductor device (See ¶[0023]). With respect to claim 34, Budd discloses wherein the trench structure includes a reflective coating, and wherein the reflective coating includes one or more of: a silicon dioxide material, a titanium dioxide material, an aluminum arsenide material, a gallium arsenide material, an aluminum nitride material, or a gallium nitride material (see ¶[0020]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Budd in view of Kropp et al. (U.S. Publication No. 2017/0373471 A1) With respect to claim 15, Budd fails to disclose wherein forming the reflector structure within the cavity comprises: forming a distributed Bragg reflector structure within the cavity. In the same field of endeavor, Kropp teaches wherein forming the reflector structure within the cavity comprises: forming a distributed Bragg reflector structure within the cavity (see ¶[0021]). Implementing a distributed Bragg reflector within the device of Budd, as taught by Kropp controls parasitic capacitance of the overall device (See ¶[0004]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention. Allowable Subject Matter Claim 11, 22-25 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. With respect to claim 11, none of the prior art teaches or suggests, alone or in combination, forming a dielectric layer on the echelle grating structure and over the substrate layer; and forming second cavity through the dielectric layer to the echelle grating structure. With respect to claims 22-23, none of the prior art teaches or suggests, alone or in combination, a segment that penetrates through a dielectric layer of the second semiconductor device and includes a gas that is transmissive to the light waves, and a distributed Bragg reflector structure on sidewalls of the segment to reflect and redirect light along a direction that is orthogonal to the bond line. With respect to claims 24-25, none of the prior art teaches or suggests, alone or in combination, a first segment that penetrates through a dielectric layer of the second semiconductor device and includes a gas that is transmissive to the light waves, and a second segment in a substrate layer of the second semiconductor device above the dielectric layer, wherein the second segment is aligned with the first segment. With respect to claim 27, none of the prior art teaches or suggests, alone or in combination, first trench structure penetrates into the second semiconductor device a first height, and wherein the second trench structure penetrates into the second semiconductor device a second height that is lesser relative to the first height. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Doany et al. (U.S. Patent No. 8,399,292 B2) discloses photodetector with a backside optical via but fails to disclose a segment that penetrates through a dielectric layer of the second semiconductor device and includes a gas that is transmissive to the light waves, and a distributed Bragg reflector structure on sidewalls of the segment to reflect and redirect light along a direction that is orthogonal to the bond line. Wood et al. (U.S. Patent No. 11,726,276 B1) discloses a photonic transceiver with echelle grating but fails to disclose forming a dielectric layer on the echelle grating structure and over the substrate layer; and forming second cavity through the dielectric layer to the echelle grating structure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN LOKE can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JONATHAN HAN/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Dec 28, 2023
Application Filed
May 02, 2024
Response after Non-Final Action
Aug 19, 2026
Non-Final Rejection mailed — §102, §103, §112
Sep 25, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

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FIELD EFFECT TRANSISTOR WITH BACKSIDE SOURCE/DRAIN
3y 12m to grant Granted Sep 29, 2026
Patent 12751273
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
3y 0m to grant Granted Sep 29, 2026
Patent 12745677
COLOR-TEMPERATURE-TUNABLE LIGHTING DEVICES
3y 1m to grant Granted Sep 22, 2026
Patent 12740437
LEAD FRAME
3y 0m to grant Granted Sep 15, 2026
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OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME
3y 1m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+9.7%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1287 resolved cases by this examiner. Grant probability derived from career allowance rate.

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